Lines Matching defs:SrcRC

195   const TargetRegisterClass *SrcRC = SrcReg.isVirtual()
200   // SrcRC = TRI.getSubRegClass(SrcRC, Copy.getOperand(1).getSubReg());
206   return std::pair(SrcRC, DstRC);
209 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC,
212   return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) &&
213          TRI.hasVectorRegisters(SrcRC);
216 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC,
219   return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) &&
285   const TargetRegisterClass *SrcRC, *DstRC;
286   std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI);
288   if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI))
313     const TargetRegisterClass *SrcRC =
315     assert(TRI->isSGPRClass(SrcRC) &&
317     const TargetRegisterClass *NewSrcRC = TRI->getEquivalentVGPRClass(SrcRC);
326       const TargetRegisterClass *NewSrcRC = TRI->getEquivalentAGPRClass(SrcRC);
630         const TargetRegisterClass *SrcRC, *DstRC;
631         std::tie(SrcRC, DstRC) = getCopyRegClasses(MI, *TRI, *MRI);
633         if (isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) {
644         if (!isVGPRToSGPRCopy(SrcRC, DstRC, *TRI))
660             const TargetRegisterClass *SrcRC = MRI->getRegClass(MO.getReg());
661             if (TRI->hasVectorRegisters(SrcRC)) {
663                   TRI->getEquivalentSGPRClass(SrcRC);
763       const TargetRegisterClass *SrcRC, *DstRC;
764       std::tie(SrcRC, DstRC) = getCopyRegClasses(*MI, *TRI, *MRI);
765       if (isSGPRToVGPRCopy(SrcRC, DstRC, *TRI))
854   const TargetRegisterClass *SrcRC =
856   unsigned MoveSize = TRI->getRegSizeInBits(*SrcRC);
1063     const TargetRegisterClass *SrcRC =
1065     size_t SrcSize = TRI->getRegSizeInBits(*SrcRC);
1078       int N = TRI->getRegSizeInBits(*SrcRC) / 32;
1081             Result, *MRI, MI->getOperand(1), SrcRC,