Lines Matching +full:0 +full:x133
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
36 SI = 0,
55 SALU = 1 << 0,
109 // Reserved, must be 0.
115 // Reserved, must be 0.
184 S_NAN = 1 << 0, // Signaling NaN
275 INT = 0,
287 NONE = 0,
288 NEG = 1 << 0, // Floating-point negate modifier
290 SEXT = 1 << 0, // Integer sign-extend modifier
300 NONE = 0,
311 ID_SRC0 = 0,
321 OFF = 0,
327 UNDEF = 0xFFFF
335 DEFAULT = 0,
348 SGPR_MIN = 0,
371 REG_IDX_MASK = 0xff,
393 TH = 0x7, // All TH bits
394 TH_RT = 0, // regular
413 SCOPE = 0x3 << 3, // All Scope bits
414 SCOPE_CU = 0 << 3,
438 enum Id { // Message ID, width(4) [3:0].
466 ID_MASK_PreGFX11_ = 0xF,
467 ID_MASK_GFX11Plus_ = 0xFF
472 OP_NONE_ = 0,
477 OP_GS_NOP = 0,
491 STREAM_ID_NONE_ = 0,
492 STREAM_ID_DEFAULT_ = 0,
504 enum Id { // HwRegCode, (6) [5:0]
557 FP_ROUND_MASK = 0xf << 0, // Bits 0..3
558 FP_DENORM_MASK = 0xf << 4, // Bits 4..7
575 CSP_MASK = 0x7u << 29 // Bits 29..31
583 DFMT_INVALID = 0,
606 DFMT_SHIFT = 0,
607 DFMT_MASK = 0xF
611 NFMT_UNORM = 0,
652 UFMT_INVALID = 0,
752 UFMT_INVALID = 0,
839 ID_QUAD_PERM = 0,
850 QUAD_PERM_ENC = 0x8000,
851 QUAD_PERM_ENC_MASK = 0xFF00,
853 BITMASK_PERM_ENC = 0x0000,
854 BITMASK_PERM_ENC_MASK = 0x8000,
858 LANE_MASK = 0x3,
865 BITMASK_MASK = 0x1F,
869 BITMASK_AND_SHIFT = 0,
879 BYTE_0 = 0,
889 UNUSED_PAD = 0,
895 SRC_SGPR_MASK = 0x100,
896 SRC_VGPR_MASK = 0xFF,
897 VOPC_DST_VCC_MASK = 0x80,
898 VOPC_DST_SGPR_MASK = 0x7F,
900 SRC_VGPR_MIN = 0,
915 QUAD_PERM_FIRST = 0,
916 QUAD_PERM_ID = 0xE4, // identity permutation
917 QUAD_PERM_LAST = 0xFF,
918 DPP_UNUSED1 = 0x100,
919 ROW_SHL0 = 0x100,
920 ROW_SHL_FIRST = 0x101,
921 ROW_SHL_LAST = 0x10F,
922 DPP_UNUSED2 = 0x110,
923 ROW_SHR0 = 0x110,
924 ROW_SHR_FIRST = 0x111,
925 ROW_SHR_LAST = 0x11F,
926 DPP_UNUSED3 = 0x120,
927 ROW_ROR0 = 0x120,
928 ROW_ROR_FIRST = 0x121,
929 ROW_ROR_LAST = 0x12F,
930 WAVE_SHL1 = 0x130,
931 DPP_UNUSED4_FIRST = 0x131,
932 DPP_UNUSED4_LAST = 0x133,
933 WAVE_ROL1 = 0x134,
934 DPP_UNUSED5_FIRST = 0x135,
935 DPP_UNUSED5_LAST = 0x137,
936 WAVE_SHR1 = 0x138,
937 DPP_UNUSED6_FIRST = 0x139,
938 DPP_UNUSED6_LAST = 0x13B,
939 WAVE_ROR1 = 0x13C,
940 DPP_UNUSED7_FIRST = 0x13D,
941 DPP_UNUSED7_LAST = 0x13F,
942 ROW_MIRROR = 0x140,
943 ROW_HALF_MIRROR = 0x141,
944 BCAST15 = 0x142,
945 BCAST31 = 0x143,
946 DPP_UNUSED8_FIRST = 0x144,
947 DPP_UNUSED8_LAST = 0x14F,
948 ROW_NEWBCAST_FIRST= 0x150,
949 ROW_NEWBCAST_LAST = 0x15F,
950 ROW_SHARE0 = 0x150,
951 ROW_SHARE_FIRST = 0x150,
952 ROW_SHARE_LAST = 0x15F,
953 ROW_XMASK0 = 0x160,
954 ROW_XMASK_FIRST = 0x160,
955 ROW_XMASK_LAST = 0x16F,
961 DPP_FI_0 = 0,
963 DPP8_FI_0 = 0xE9,
964 DPP8_FI_1 = 0xEA,
972 ET_MRT0 = 0,
986 ET_NULL_MAX_IDX = 0,
987 ET_MRTZ_MAX_IDX = 0,
988 ET_PRIM_MAX_IDX = 0,
1031 WWM_REG = 1 << 0,
1046 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
1047 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
1048 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
1049 #define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
1050 #define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1051 #define C_00B028_MEM_ORDERED 0xFDFFFFFF
1053 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
1054 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
1055 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
1056 #define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
1057 #define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
1058 #define C_00B128_MEM_ORDERED 0xF7FFFFFF
1060 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
1061 #define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
1062 #define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
1063 #define C_00B228_WGP_MODE 0xF7FFFFFF
1064 #define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
1065 #define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1066 #define C_00B228_MEM_ORDERED 0xFDFFFFFF
1068 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
1069 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
1070 #define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
1071 #define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
1072 #define C_00B428_WGP_MODE 0xFBFFFFFF
1073 #define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
1074 #define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
1075 #define C_00B428_MEM_ORDERED 0xFEFFFFFF
1077 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
1079 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
1080 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
1081 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
1082 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
1083 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
1084 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
1085 #define C_00B84C_USER_SGPR 0xFFFFFFC1
1086 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
1087 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
1088 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
1089 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
1090 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
1091 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
1092 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
1093 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
1094 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
1095 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
1096 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
1097 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
1098 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
1099 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
1100 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
1101 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
1102 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
1103 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
1105 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
1106 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
1107 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
1109 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
1110 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
1111 #define C_00B84C_LDS_SIZE 0xFF007FFF
1112 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
1113 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
1114 #define C_00B84C_EXCP_EN 0x80FFFFFF
1116 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
1117 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
1119 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
1120 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
1121 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
1122 #define C_00B848_VGPRS 0xFFFFFFC0
1123 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
1124 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
1125 #define C_00B848_SGPRS 0xFFFFFC3F
1126 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
1127 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
1128 #define C_00B848_PRIORITY 0xFFFFF3FF
1129 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
1130 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
1131 #define C_00B848_FLOAT_MODE 0xFFF00FFF
1132 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
1133 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
1134 #define C_00B848_PRIV 0xFFEFFFFF
1135 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
1136 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
1137 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
1138 #define S_00B848_RR_WG_MODE(x) (((x) & 0x1) << 21)
1139 #define G_00B848_RR_WG_MODE(x) (((x) >> 21) & 0x1)
1140 #define C_00B848_RR_WG_MODE 0xFFDFFFFF
1141 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
1142 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
1143 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
1144 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
1145 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
1146 #define C_00B848_IEEE_MODE 0xFF7FFFFF
1147 #define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
1148 #define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
1149 #define C_00B848_WGP_MODE 0xDFFFFFFF
1150 #define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
1151 #define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
1152 #define C_00B848_MEM_ORDERED 0xBFFFFFFF
1153 #define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
1154 #define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
1155 #define C_00B848_FWD_PROGRESS 0x7FFFFFFF
1158 #define FP_ROUND_ROUND_TO_NEAREST 0
1163 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
1165 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
1166 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
1168 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
1176 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
1177 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
1179 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
1180 #define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1181 #define S_00B860_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1182 #define S_00B860_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1184 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
1185 #define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1186 #define S_0286E8_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1187 #define S_0286E8_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1189 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
1190 #define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
1191 #define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
1192 #define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
1193 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
1194 #define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
1195 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
1196 #define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
1198 #define R_SPILLED_SGPRS 0x4
1199 #define R_SPILLED_VGPRS 0x8