Lines Matching defs:MemVT

1039   EVT MemVT = Store->getMemoryVT();
1072   SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1113   EVT MemVT = StoreNode->getMemoryVT();
1129           NewChain, DL, Value, Ptr, StoreNode->getPointerInfo(), MemVT,
1139   if (Alignment < MemVT.getStoreSize() &&
1140       !allowsMisalignedMemoryAccesses(MemVT, AS, Alignment,
1155       if (MemVT == MVT::i8) {
1158         assert(MemVT == MVT::i16);
1186                                      Op->getVTList(), Args, MemVT,
1206   if (MemVT.bitsLT(MVT::i32))
1266   EVT MemVT = Load->getMemoryVT();
1267   assert(Load->getAlign() >= MemVT.getStoreSize());
1300   EVT MemEltVT = MemVT.getScalarType();
1320   EVT MemVT = LoadNode->getMemoryVT();
1324       ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) {
1380     assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1382         ISD::EXTLOAD, DL, VT, Chain, Ptr, LoadNode->getPointerInfo(), MemVT,
1385                               DAG.getValueType(MemVT));
1474     EVT MemVT = VA.getLocVT();
1475     if (!VT.isVector() && MemVT.isVector()) {
1477       MemVT = MemVT.getVectorElementType();
1495     if (MemVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) {
1515         MemVT, Alignment, MachineMemOperand::MONonTemporal |
1531 bool R600TargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
1535     return (MemVT.getSizeInBits() <= 32);