Lines Matching defs:DL
430 SDLoc DL(Op);
436 DAG.getConstant(0, DL, MVT::i32), // SWZ_X
437 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y
438 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z
439 DAG.getConstant(3, DL, MVT::i32) // SWZ_W
441 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args);
453 SDLoc DL(Op);
470 DAG.getConstant(TextureOp, DL, MVT::i32),
472 DAG.getConstant(0, DL, MVT::i32),
473 DAG.getConstant(1, DL, MVT::i32),
474 DAG.getConstant(2, DL, MVT::i32),
475 DAG.getConstant(3, DL, MVT::i32),
479 DAG.getConstant(0, DL, MVT::i32),
480 DAG.getConstant(1, DL, MVT::i32),
481 DAG.getConstant(2, DL, MVT::i32),
482 DAG.getConstant(3, DL, MVT::i32),
490 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
494 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
495 DAG.getConstant(0, DL, MVT::i32)),
496 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
497 DAG.getConstant(0, DL, MVT::i32)),
498 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
499 DAG.getConstant(1, DL, MVT::i32)),
500 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
501 DAG.getConstant(1, DL, MVT::i32)),
502 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
503 DAG.getConstant(2, DL, MVT::i32)),
504 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
505 DAG.getConstant(2, DL, MVT::i32)),
506 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
507 DAG.getConstant(3, DL, MVT::i32)),
508 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
509 DAG.getConstant(3, DL, MVT::i32))
511 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args);
517 return DAG.getConstant(ByteOffset, DL, PtrVT);
520 return LowerImplicitParameter(DAG, VT, DL, 0);
522 return LowerImplicitParameter(DAG, VT, DL, 1);
524 return LowerImplicitParameter(DAG, VT, DL, 2);
526 return LowerImplicitParameter(DAG, VT, DL, 3);
528 return LowerImplicitParameter(DAG, VT, DL, 4);
530 return LowerImplicitParameter(DAG, VT, DL, 5);
532 return LowerImplicitParameter(DAG, VT, DL, 6);
534 return LowerImplicitParameter(DAG, VT, DL, 7);
536 return LowerImplicitParameter(DAG, VT, DL, 8);
564 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
567 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1));
623 SDLoc DL(Vector);
629 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vector,
630 DAG.getVectorIdxConstant(i, DL)));
633 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args);
638 SDLoc DL(Op);
647 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(),
653 SDLoc DL(Op);
663 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(),
675 const DataLayout &DL = DAG.getDataLayout();
677 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
688 SDLoc DL(Op);
691 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT,
692 DAG.getNode(ISD::FADD, DL, VT,
693 DAG.getNode(ISD::FMUL, DL, VT, Arg,
694 DAG.getConstantFP(0.15915494309, DL, MVT::f32)),
695 DAG.getConstantFP(0.5, DL, MVT::f32)));
707 SDValue TrigVal = DAG.getNode(TrigNode, DL, VT,
708 DAG.getNode(ISD::FADD, DL, VT, FractPart,
709 DAG.getConstantFP(-0.5, DL, MVT::f32)));
713 return DAG.getNode(ISD::FMUL, DL, VT, TrigVal,
714 DAG.getConstantFP(numbers::pif, DL, MVT::f32));
726 SDLoc DL(Op);
732 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi);
734 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF,
737 SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi);
739 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF);
743 SDLoc DL(Op);
746 DL,
748 Op, DAG.getConstantFP(1.0f, DL, MVT::f32),
753 SDLoc DL(Op);
756 DL,
758 Op, DAG.getConstantFP(-1.0f, DL, MVT::f32),
763 const SDLoc &DL,
772 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
773 DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR
800 SDLoc DL(Op);
812 SDValue MinMax = combineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
851 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
892 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
893 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
908 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
912 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
920 HWTrue = DAG.getConstantFP(1.0f, DL, CompareVT);
921 HWFalse = DAG.getConstantFP(0.0f, DL, CompareVT);
923 HWTrue = DAG.getConstant(-1, DL, CompareVT);
924 HWFalse = DAG.getConstant(0, DL, CompareVT);
932 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
934 return DAG.getNode(ISD::SELECT_CC, DL, VT,
980 SDLoc DL(Ptr);
981 return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr,
982 DAG.getConstant(SRLPad, DL, MVT::i32));
1016 SDLoc DL(Store);
1025 Mask = DAG.getConstant(0xff, DL, MVT::i32);
1028 Mask = DAG.getConstant(0xffff, DL, MVT::i32);
1043 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset);
1048 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1049 DAG.getConstant(0xfffffffc, DL, MVT::i32));
1054 SDValue Dst = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo);
1059 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1060 DAG.getConstant(0x3, DL, MVT::i32));
1063 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1064 DAG.getConstant(3, DL, MVT::i32));
1068 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1072 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1075 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1079 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt);
1083 DstMask = DAG.getNOT(DL, DstMask, MVT::i32);
1086 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1089 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1093 SDValue NewStore = DAG.getStore(Chain, DL, Value, Ptr, PtrInfo);
1098 Chain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, NewStore);
1116 SDLoc DL(Op);
1126 SDValue NewChain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, Chain);
1129 NewChain, DL, Value, Ptr, StoreNode->getPointerInfo(), MemVT,
1146 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, PtrVT, Ptr,
1147 DAG.getConstant(2, DL, PtrVT));
1156 MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32);
1160 MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32);
1163 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, PtrVT, Ptr,
1164 DAG.getConstant(0x00000003, DL, PtrVT));
1165 SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1166 DAG.getConstant(3, DL, VT));
1169 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, BitShift);
1172 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
1173 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, BitShift);
1179 DAG.getConstant(0, DL, MVT::i32),
1180 DAG.getConstant(0, DL, MVT::i32),
1183 SDValue Input = DAG.getBuildVector(MVT::v4i32, DL, Src);
1185 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
1191 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr);
1196 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1212 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr);
1213 return DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1263 SDLoc DL(Op);
1275 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset);
1280 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr,
1281 DAG.getConstant(0xfffffffc, DL, MVT::i32));
1286 SDValue Read = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo);
1289 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1290 LoadPtr, DAG.getConstant(0x3, DL, MVT::i32));
1293 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1294 DAG.getConstant(3, DL, MVT::i32));
1297 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt);
1304 Ret = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode);
1306 Ret = DAG.getZeroExtendInReg(Ret, DL, MemEltVT);
1314 return DAG.getMergeValues(Ops, DL);
1328 SDLoc DL(Op);
1338 return DAG.getMergeValues(Ops, DL);
1353 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1354 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1355 DAG.getConstant(4, DL, MVT::i32)),
1358 DL, MVT::i32));
1361 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1362 DAG.getConstant(0, DL, MVT::i32));
1369 return DAG.getMergeValues(MergedValues, DL);
1382 ISD::EXTLOAD, DL, VT, Chain, Ptr, LoadNode->getPointerInfo(), MemVT,
1384 SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad,
1388 return DAG.getMergeValues(MergedValues, DL);
1398 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(2, DL, MVT::i32));
1399 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, MVT::i32, Ptr);
1400 return DAG.getLoad(MVT::i32, DL, Chain, Ptr, LoadNode->getMemOperand());
1456 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
1482 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
1512 ISD::UNINDEXED, Ext, VT, DL, Chain,
1513 DAG.getConstant(PartOffset, DL, MVT::i32), DAG.getUNDEF(MVT::i32),
1524 EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1564 SDLoc DL(VectorEntry);
1569 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry,
1570 DAG.getIntPtrConstant(i, DL));
1608 SDLoc DL(VectorEntry);
1614 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry,
1615 DAG.getIntPtrConstant(i, DL));
1644 const SDLoc &DL) const {
1652 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
1660 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
1668 SDLoc DL(LoadNode);
1690 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1691 DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32));
1692 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1700 SDValue Result = DAG.getBuildVector(NewVT, DL, ArrayRef(Slots, NumElements));
1702 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1703 DAG.getConstant(0, DL, MVT::i32));
1709 return DAG.getMergeValues(MergedValues, DL);
1719 SDLoc DL(N);
1726 return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0),
1751 return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0),
1754 DAG.getConstant(-1, DL, MVT::i32), // True
1755 DAG.getConstant(0, DL, MVT::i32), // False
1802 DAG.getNode(ISD::ANY_EXTEND, DL, OpVT, InVal) :
1803 DAG.getNode(ISD::TRUNCATE, DL, OpVT, InVal);
1808 return DAG.getBuildVector(VT, DL, Ops);
1827 return DAG.getNode(ISD::BITCAST, DL, N->getVTList(),
1868 return DAG.getSelectCC(DL,
1895 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG, DL);
1896 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, N->getVTList(), NewArgs);
1924 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG, DL);
1925 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, N->getVTList(), NewArgs);