Lines Matching defs:OpNo
52 void getMachineOpValueT16(const MCInst &MI, unsigned OpNo, APInt &Op,
56 void getMachineOpValueT16Lo128(const MCInst &MI, unsigned OpNo, APInt &Op,
62 void getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
66 void getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
70 void getSDWASrcEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
74 void getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
78 void getAVOperandEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
85 unsigned OpNo, APInt &Op,
456 void AMDGPUMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
460 const MCOperand &MO = MI.getOperand(OpNo);
473 const MCInst &MI, unsigned OpNo, APInt &Op,
475 auto Offset = MI.getOperand(OpNo).getImm();
481 void AMDGPUMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
489 const MCOperand &MO = MI.getOperand(OpNo);
502 auto Enc = getLitEncoding(MO, Desc.operands()[OpNo], STI);
513 const MCInst &MI, unsigned OpNo, APInt &Op,
519 const MCOperand &MO = MI.getOperand(OpNo);
531 const MCInst &MI, unsigned OpNo, APInt &Op,
533 unsigned Reg = MI.getOperand(OpNo).getReg();
595 unsigned OpNo = &MO - MI.begin();
596 getMachineOpValueCommon(MI, MO, OpNo, Op, Fixups, STI);
600 const MCInst &MI, unsigned OpNo, APInt &Op,
602 const MCOperand &MO = MI.getOperand(OpNo);
610 getMachineOpValueCommon(MI, MO, OpNo, Op, Fixups, STI);
616 assert(OpNo < INT_MAX);
617 if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI.getOpcode(),
627 } else if ((int)OpNo == AMDGPU::getNamedOperandIdx(
630 else if ((int)OpNo == AMDGPU::getNamedOperandIdx(
647 const MCInst &MI, unsigned OpNo, APInt &Op,
649 const MCOperand &MO = MI.getOperand(OpNo);
659 getMachineOpValueCommon(MI, MO, OpNo, Op, Fixups, STI);
663 const MCInst &MI, const MCOperand &MO, unsigned OpNo, APInt &Op,
696 if (AMDGPU::isSISrcOperand(Desc, OpNo)) {
697 if (auto Enc = getLitEncoding(MO, Desc.operands()[OpNo], STI)) {