Lines Matching full:cpol
186 const int64_t TH = Imm & CPol::TH;
187 const int64_t Scope = Imm & CPol::SCOPE;
195 if (Imm & CPol::GLC)
199 if (Imm & CPol::SLC)
201 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
203 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
205 if (Imm & ~CPol::ALL)
225 if (TH & AMDGPU::CPol::TH_ATOMIC_CASCADE) {
226 if (Scope >= AMDGPU::CPol::SCOPE_DEV)
227 O << "CASCADE" << (TH & AMDGPU::CPol::TH_ATOMIC_NT ? "_NT" : "_RT");
230 } else if (TH & AMDGPU::CPol::TH_ATOMIC_NT)
231 O << "NT" << (TH & AMDGPU::CPol::TH_ATOMIC_RETURN ? "_RETURN" : "");
232 else if (TH & AMDGPU::CPol::TH_ATOMIC_RETURN)
237 if (!IsStore && TH == AMDGPU::CPol::TH_RESERVED)
245 case AMDGPU::CPol::TH_NT:
248 case AMDGPU::CPol::TH_HT:
251 case AMDGPU::CPol::TH_BYPASS: // or LU or RT_WB
252 O << (Scope == AMDGPU::CPol::SCOPE_SYS ? "BYPASS"
255 case AMDGPU::CPol::TH_NT_RT:
258 case AMDGPU::CPol::TH_RT_NT:
261 case AMDGPU::CPol::TH_NT_HT:
264 case AMDGPU::CPol::TH_NT_WB:
275 if (Scope == CPol::SCOPE_CU)
280 if (Scope == CPol::SCOPE_SE)
282 else if (Scope == CPol::SCOPE_DEV)
284 else if (Scope == CPol::SCOPE_SYS)