Lines Matching defs:STI
44 StringRef Annot, const MCSubtargetInfo &STI,
46 printInstruction(MI, Address, STI, OS);
51 const MCSubtargetInfo &STI,
57 const MCSubtargetInfo &STI,
71 printU32ImmOperand(MI, OpNo, STI, O);
90 const MCSubtargetInfo &STI,
103 const MCSubtargetInfo &STI,
112 if (AMDGPU::isGFX12(STI) && IsVBuffer)
120 const MCSubtargetInfo &STI,
129 AMDGPU::isGFX12(STI);
132 O << formatDec(SignExtend32(Imm, AMDGPU::getNumFlatOffsetBits(STI)));
139 const MCSubtargetInfo &STI,
148 const MCSubtargetInfo &STI,
157 const MCSubtargetInfo &STI,
159 printU32ImmOperand(MI, OpNo, STI, O);
163 const MCSubtargetInfo &STI,
169 const MCSubtargetInfo &STI,
172 printSMEMOffset(MI, OpNo, STI, O);
176 const MCSubtargetInfo &STI,
178 printU32ImmOperand(MI, OpNo, STI, O);
182 const MCSubtargetInfo &STI, raw_ostream &O) {
185 if (AMDGPU::isGFX12Plus(STI)) {
196 O << ((AMDGPU::isGFX940(STI) &&
200 O << (AMDGPU::isGFX940(STI) ? " nt" : " slc");
201 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
203 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
204 O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc");
293 const MCSubtargetInfo &STI, raw_ostream &O) {
296 printU16ImmOperand(MI, OpNo, STI, O);
301 const MCSubtargetInfo &STI, raw_ostream &O) {
313 const MCSubtargetInfo &STI, raw_ostream &O) {
314 if (STI.hasFeature(AMDGPU::FeatureR128A16))
321 const MCSubtargetInfo &STI,
326 const MCSubtargetInfo &STI,
335 if (AMDGPU::isGFX10Plus(STI)) {
338 if (isValidUnifiedFormat(Val, STI)) {
339 O << " format:[" << getUnifiedFormatName(Val, STI) << ']';
346 if (isValidDfmtNfmt(Val, STI)) {
358 O << getNfmtName(Nfmt, STI);
386 const MCSubtargetInfo &STI, raw_ostream &O) {
405 printRegularOperand(MI, OpNo, STI, O);
441 printDefaultVccOperand(false, STI, O);
447 const MCSubtargetInfo &STI, raw_ostream &O) {
448 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
453 printRegularOperand(MI, OpNo, STI, O);
457 const MCSubtargetInfo &STI,
465 if (printImmediateFloat32(Imm, STI, O))
471 static bool printImmediateFP16(uint32_t Imm, const MCSubtargetInfo &STI,
489 else if (Imm == 0x3118 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
497 static bool printImmediateBFloat16(uint32_t Imm, const MCSubtargetInfo &STI,
515 else if (Imm == 0x3E22 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
524 const MCSubtargetInfo &STI,
532 if (printImmediateBFloat16(static_cast<uint16_t>(Imm), STI, O))
539 const MCSubtargetInfo &STI,
548 if (printImmediateFP16(HImm, STI, O))
556 const MCSubtargetInfo &STI,
568 if (printImmediateFloat32(Imm, STI, O))
575 printImmediateFP16(static_cast<uint16_t>(Imm), STI, O))
582 printImmediateBFloat16(static_cast<uint16_t>(Imm), STI, O))
593 const MCSubtargetInfo &STI,
614 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
623 const MCSubtargetInfo &STI,
631 if (printImmediateFloat32(Imm, STI, O))
638 const MCSubtargetInfo &STI,
665 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
680 const MCSubtargetInfo &STI,
686 if (AMDGPU::isGFX940(STI)) {
702 const MCSubtargetInfo &STI,
712 const MCSubtargetInfo &STI,
722 const MCSubtargetInfo &STI,
726 printRegOperand(STI.hasFeature(AMDGPU::FeatureWavefrontSize64)
735 const MCSubtargetInfo &STI,
742 const MCSubtargetInfo &STI,
749 const MCSubtargetInfo &STI,
756 const MCSubtargetInfo &STI,
773 const MCSubtargetInfo &STI,
786 printDefaultVccOperand(true, STI, O);
788 printRegularOperand(MI, OpNo, STI, O);
793 const MCSubtargetInfo &STI,
834 printImmediate32(Op.getImm(), STI, O);
838 printImmediate64(Op.getImm(), STI, O, false);
843 printImmediate64(Op.getImm(), STI, O, true);
848 printImmediateInt16(Op.getImm(), STI, O);
854 printImmediateF16(Op.getImm(), STI, O);
860 printImmediateBF16(Op.getImm(), STI, O);
871 printImmediateV216(Op.getImm(), OpTy, STI, O);
880 printImmediate32(Op.getImm(), STI, O);
898 printImmediate32(llvm::bit_cast<uint32_t>((float)Value), STI, O);
900 printImmediate64(llvm::bit_cast<uint64_t>(Value), STI, O, true);
954 printDefaultVccOperand(OpNo == 0, STI, O);
963 printSymbolicFormat(MI, STI, O);
969 const MCSubtargetInfo &STI,
973 printDefaultVccOperand(true, STI, O);
997 printRegularOperand(MI, OpNo + 1, STI, O);
1015 printDefaultVccOperand(OpNo == 0, STI, O);
1022 const MCSubtargetInfo &STI,
1026 printDefaultVccOperand(true, STI, O);
1031 printRegularOperand(MI, OpNo + 1, STI, O);
1044 printDefaultVccOperand(OpNo == 0, STI, O);
1050 const MCSubtargetInfo &STI,
1052 if (!AMDGPU::isGFX10Plus(STI))
1064 const MCSubtargetInfo &STI,
1094 if (AMDGPU::isGFX10Plus(STI)) {
1100 if (AMDGPU::isGFX10Plus(STI)) {
1106 if (AMDGPU::isGFX10Plus(STI)) {
1112 if (AMDGPU::isGFX10Plus(STI)) {
1122 if (AMDGPU::isGFX10Plus(STI)) {
1128 if (AMDGPU::isGFX10Plus(STI)) {
1135 if (AMDGPU::isGFX90A(STI)) {
1137 } else if (AMDGPU::isGFX10Plus(STI)) {
1147 if (!AMDGPU::isGFX10Plus(STI)) {
1159 const MCSubtargetInfo &STI,
1162 printU4ImmOperand(MI, OpNo, STI, O);
1166 const MCSubtargetInfo &STI,
1169 printU4ImmOperand(MI, OpNo, STI, O);
1173 const MCSubtargetInfo &STI,
1182 const MCSubtargetInfo &STI, raw_ostream &O) {
1208 const MCSubtargetInfo &STI,
1215 const MCSubtargetInfo &STI,
1222 const MCSubtargetInfo &STI,
1229 const MCSubtargetInfo &STI,
1244 const MCSubtargetInfo &STI, raw_ostream &O,
1263 const MCSubtargetInfo &STI,
1265 printExpSrcN(MI, OpNo, STI, O, 0);
1269 const MCSubtargetInfo &STI,
1271 printExpSrcN(MI, OpNo, STI, O, 1);
1275 const MCSubtargetInfo &STI,
1277 printExpSrcN(MI, OpNo, STI, O, 2);
1281 const MCSubtargetInfo &STI,
1283 printExpSrcN(MI, OpNo, STI, O, 3);
1287 const MCSubtargetInfo &STI,
1296 if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) {
1387 const MCSubtargetInfo &STI,
1414 const MCSubtargetInfo &STI,
1420 const MCSubtargetInfo &STI,
1426 const MCSubtargetInfo &STI,
1432 const MCSubtargetInfo &STI,
1442 const MCSubtargetInfo &STI,
1452 const MCSubtargetInfo &STI,
1471 const MCSubtargetInfo &STI,
1478 const MCSubtargetInfo &STI,
1485 const MCSubtargetInfo &STI,
1508 const MCSubtargetInfo &STI,
1510 printRegularOperand(MI, OpNo, STI, O);
1512 printRegularOperand(MI, OpNo + 1, STI, O);
1536 const MCSubtargetInfo &STI,
1548 const MCSubtargetInfo &STI,
1557 decodeMsg(Imm16, MsgId, OpId, StreamId, STI);
1559 StringRef MsgName = getMsgName(MsgId, STI);
1561 if (!MsgName.empty() && isValidMsgOp(MsgId, OpId, STI) &&
1562 isValidMsgStream(MsgId, OpId, StreamId, STI)) {
1564 if (msgRequiresOp(MsgId, STI)) {
1565 O << ", " << getMsgOpName(MsgId, OpId, STI);
1566 if (msgSupportsStream(MsgId, OpId, STI)) {
1612 const MCSubtargetInfo &STI,
1682 const MCSubtargetInfo &STI,
1684 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());
1717 const MCSubtargetInfo &STI,
1724 if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) {
1730 while (decodeDepCtr(Imm16, Id, Name, Val, IsDefault, STI)) {
1744 const MCSubtargetInfo &STI,
1787 const MCSubtargetInfo &STI, raw_ostream &O) {
1791 StringRef HwRegName = getHwreg(Id, STI);
1805 const MCSubtargetInfo &STI,
1816 const MCSubtargetInfo &STI,