Lines Matching defs:O
52 raw_ostream &O) {
53 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
58 raw_ostream &O) {
61 Op.getExpr()->print(O, &MAI);
69 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
71 printU32ImmOperand(MI, OpNo, STI, O);
75 raw_ostream &O) {
76 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
80 raw_ostream &O) {
81 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
85 raw_ostream &O) {
86 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
91 raw_ostream &O) {
92 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
96 raw_ostream &O, StringRef BitName) {
98 O << ' ' << BitName;
104 raw_ostream &O) {
107 O << " offset:";
113 O << formatDec(SignExtend32<24>(Imm));
115 printU16ImmDecOperand(MI, OpNo, O);
121 raw_ostream &O) {
124 O << " offset:";
132 O << formatDec(SignExtend32(Imm, AMDGPU::getNumFlatOffsetBits(STI)));
134 printU16ImmDecOperand(MI, OpNo, O);
140 raw_ostream &O) {
142 O << " offset0:";
143 printU8ImmDecOperand(MI, OpNo, O);
149 raw_ostream &O) {
151 O << " offset1:";
152 printU8ImmDecOperand(MI, OpNo, O);
158 raw_ostream &O) {
159 printU32ImmOperand(MI, OpNo, STI, O);
164 raw_ostream &O) {
165 O << formatHex(MI->getOperand(OpNo).getImm());
170 raw_ostream &O) {
171 O << " offset:";
172 printSMEMOffset(MI, OpNo, STI, O);
177 raw_ostream &O) {
178 printU32ImmOperand(MI, OpNo, STI, O);
182 const MCSubtargetInfo &STI, raw_ostream &O) {
189 printTH(MI, TH, Scope, O);
190 printScope(Scope, O);
196 O << ((AMDGPU::isGFX940(STI) &&
200 O << (AMDGPU::isGFX940(STI) ? " nt" : " slc");
202 O << " dlc";
204 O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc");
206 O << " /* unexpected cache policy bit */";
210 raw_ostream &O) {
221 O << " th:";
224 O << "TH_ATOMIC_";
227 O << "CASCADE" << (TH & AMDGPU::CPol::TH_ATOMIC_NT ? "_NT" : "_RT");
229 O << formatHex(TH);
231 O << "NT" << (TH & AMDGPU::CPol::TH_ATOMIC_RETURN ? "_RETURN" : "");
233 O << "RETURN";
235 O << formatHex(TH);
238 O << formatHex(TH);
243 O << (IsStore ? "TH_STORE_" : "TH_LOAD_");
246 O << "NT";
249 O << "HT";
252 O << (Scope == AMDGPU::CPol::SCOPE_SYS ? "BYPASS"
256 O << "NT_RT";
259 O << "RT_NT";
262 O << "NT_HT";
265 O << "NT_WB";
274 void AMDGPUInstPrinter::printScope(int64_t Scope, raw_ostream &O) {
278 O << " scope:";
281 O << "SCOPE_SE";
283 O << "SCOPE_DEV";
285 O << "SCOPE_SYS";
293 const MCSubtargetInfo &STI, raw_ostream &O) {
295 O << " dmask:";
296 printU16ImmOperand(MI, OpNo, STI, O);
301 const MCSubtargetInfo &STI, raw_ostream &O) {
303 O << " dim:SQ_RSRC_IMG_";
307 O << DimInfo->AsmSuffix;
309 O << Dim;
313 const MCSubtargetInfo &STI, raw_ostream &O) {
315 printNamedBit(MI, OpNo, O, "a16");
317 printNamedBit(MI, OpNo, O, "r128");
322 raw_ostream &O) {
327 raw_ostream &O) {
339 O << " format:[" << getUnifiedFormatName(Val, STI) << ']';
341 O << " format:" << Val;
350 O << " format:[";
352 O << getDfmtName(Dfmt);
354 O << ',';
358 O << getNfmtName(Nfmt, STI);
360 O << ']';
362 O << " format:" << Val;
367 void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
382 O << getRegisterName(RegNo);
386 const MCSubtargetInfo &STI, raw_ostream &O) {
391 O << "_e64_dpp";
394 O << "_e64";
396 O << "_dpp";
398 O << "_sdwa";
401 O << "_e32";
402 O << " ";
405 printRegularOperand(MI, OpNo, STI, O);
441 printDefaultVccOperand(false, STI, O);
447 const MCSubtargetInfo &STI, raw_ostream &O) {
449 O << " ";
451 O << "_e32 ";
453 printRegularOperand(MI, OpNo, STI, O);
458 raw_ostream &O) {
461 O << SImm;
465 if (printImmediateFloat32(Imm, STI, O))
468 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
472 raw_ostream &O) {
474 O << "1.0";
476 O << "-1.0";
478 O << "0.5";
480 O << "-0.5";
482 O << "2.0";
484 O << "-2.0";
486 O << "4.0";
488 O << "-4.0";
490 O << "0.15915494";
498 raw_ostream &O) {
500 O << "1.0";
502 O << "-1.0";
504 O << "0.5";
506 O << "-0.5";
508 O << "2.0";
510 O << "-2.0";
512 O << "4.0";
514 O << "-4.0";
516 O << "0.15915494";
525 raw_ostream &O) {
528 O << SImm;
532 if (printImmediateBFloat16(static_cast<uint16_t>(Imm), STI, O))
535 O << formatHex(static_cast<uint64_t>(Imm));
540 raw_ostream &O) {
543 O << SImm;
548 if (printImmediateFP16(HImm, STI, O))
552 O << formatHex(Imm16);
557 raw_ostream &O) {
560 O << SImm;
568 if (printImmediateFloat32(Imm, STI, O))
575 printImmediateFP16(static_cast<uint16_t>(Imm), STI, O))
582 printImmediateBFloat16(static_cast<uint16_t>(Imm), STI, O))
589 O << formatHex(static_cast<uint64_t>(Imm));
594 raw_ostream &O) {
596 O << "0.0";
598 O << "1.0";
600 O << "-1.0";
602 O << "0.5";
604 O << "-0.5";
606 O << "2.0";
608 O << "-2.0";
610 O << "4.0";
612 O << "-4.0";
615 O << "0.15915494";
624 raw_ostream &O) {
627 O << SImm;
631 if (printImmediateFloat32(Imm, STI, O))
634 O << formatHex(static_cast<uint64_t>(Imm));
639 raw_ostream &O, bool IsFP) {
642 O << SImm;
647 O << "0.0";
649 O << "1.0";
651 O << "-1.0";
653 O << "0.5";
655 O << "-0.5";
657 O << "2.0";
659 O << "-2.0";
661 O << "4.0";
663 O << "-4.0";
666 O << "0.15915494309189532";
669 O << formatHex(static_cast<uint64_t>(Hi_32(Imm)));
675 O << formatHex(static_cast<uint64_t>(Imm));
681 raw_ostream &O) {
692 O << " neg:[" << (Imm & 1) << ',' << ((Imm >> 1) & 1) << ','
698 O << " blgp:" << Imm;
703 raw_ostream &O) {
708 O << " cbsz:" << Imm;
713 raw_ostream &O) {
718 O << " abid:" << Imm;
723 raw_ostream &O) {
725 O << ", ";
729 O, MRI);
731 O << ", ";
736 raw_ostream &O) {
737 O << " wait_vdst:";
738 printU4ImmDecOperand(MI, OpNo, O);
743 raw_ostream &O) {
744 O << " wait_va_vdst:";
745 printU4ImmDecOperand(MI, OpNo, O);
750 raw_ostream &O) {
751 O << " wait_vm_vsrc:";
752 printU4ImmDecOperand(MI, OpNo, O);
757 raw_ostream &O) {
758 O << " wait_exp:";
759 printU4ImmDecOperand(MI, OpNo, O);
774 raw_ostream &O) {
786 printDefaultVccOperand(true, STI, O);
788 printRegularOperand(MI, OpNo, STI, O);
794 raw_ostream &O) {
798 O << "/*Missing OP" << OpNo << "*/";
804 printRegOperand(Op.getReg(), O, MRI);
814 O << "/*Invalid register, operand has \'" << MRI.getRegClassName(&RC)
834 printImmediate32(Op.getImm(), STI, O);
838 printImmediate64(Op.getImm(), STI, O, false);
843 printImmediate64(Op.getImm(), STI, O, true);
848 printImmediateInt16(Op.getImm(), STI, O);
854 printImmediateF16(Op.getImm(), STI, O);
860 printImmediateBF16(Op.getImm(), STI, O);
871 printImmediateV216(Op.getImm(), OpTy, STI, O);
875 O << formatDec(Op.getImm());
880 printImmediate32(Op.getImm(), STI, O);
881 O << "/*Invalid immediate*/";
892 O << "0.0";
898 printImmediate32(llvm::bit_cast<uint32_t>((float)Value), STI, O);
900 printImmediate64(llvm::bit_cast<uint64_t>(Value), STI, O, true);
906 Exp->print(O, &MAI);
908 O << "/*INV_OP*/";
954 printDefaultVccOperand(OpNo == 0, STI, O);
963 printSymbolicFormat(MI, STI, O);
970 raw_ostream &O) {
973 printDefaultVccOperand(true, STI, O);
989 O << "neg(";
991 O << '-';
996 O << '|';
997 printRegularOperand(MI, OpNo + 1, STI, O);
999 O << '|';
1002 O << ')';
1015 printDefaultVccOperand(OpNo == 0, STI, O);
1023 raw_ostream &O) {
1026 printDefaultVccOperand(true, STI, O);
1030 O << "sext(";
1031 printRegularOperand(MI, OpNo + 1, STI, O);
1033 O << ')';
1044 printDefaultVccOperand(OpNo == 0, STI, O);
1051 raw_ostream &O) {
1056 O << "dpp8:[" << formatDec(Imm & 0x7);
1058 O << ',' << formatDec((Imm >> (3 * i)) & 0x7);
1060 O << ']';
1065 raw_ostream &O) {
1072 O << " /* DP ALU dpp only supports row_newbcast */";
1076 O << "quad_perm:[";
1077 O << formatDec(Imm & 0x3) << ',';
1078 O << formatDec((Imm & 0xc) >> 2) << ',';
1079 O << formatDec((Imm & 0x30) >> 4) << ',';
1080 O << formatDec((Imm & 0xc0) >> 6) << ']';
1083 O << "row_shl:";
1084 printU4ImmDecOperand(MI, OpNo, O);
1087 O << "row_shr:";
1088 printU4ImmDecOperand(MI, OpNo, O);
1091 O << "row_ror:";
1092 printU4ImmDecOperand(MI, OpNo, O);
1095 O << "/* wave_shl is not supported starting from GFX10 */";
1098 O << "wave_shl:1";
1101 O << "/* wave_rol is not supported starting from GFX10 */";
1104 O << "wave_rol:1";
1107 O << "/* wave_shr is not supported starting from GFX10 */";
1110 O << "wave_shr:1";
1113 O << "/* wave_ror is not supported starting from GFX10 */";
1116 O << "wave_ror:1";
1118 O << "row_mirror";
1120 O << "row_half_mirror";
1123 O << "/* row_bcast is not supported starting from GFX10 */";
1126 O << "row_bcast:15";
1129 O << "/* row_bcast is not supported starting from GFX10 */";
1132 O << "row_bcast:31";
1136 O << "row_newbcast:";
1138 O << "row_share:";
1140 O << " /* row_newbcast/row_share is not supported on ASICs earlier "
1144 printU4ImmDecOperand(MI, OpNo, O);
1148 O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
1151 O << "row_xmask:";
1152 printU4ImmDecOperand(MI, OpNo, O);
1154 O << "/* Invalid dpp_ctrl value */";
1160 raw_ostream &O) {
1161 O << " row_mask:";
1162 printU4ImmOperand(MI, OpNo, STI, O);
1167 raw_ostream &O) {
1168 O << " bank_mask:";
1169 printU4ImmOperand(MI, OpNo, STI, O);
1174 raw_ostream &O) {
1177 O << " bound_ctrl:1";
1182 const MCSubtargetInfo &STI, raw_ostream &O) {
1186 O << " fi:1";
1191 raw_ostream &O) {
1196 case SdwaSel::BYTE_0: O << "BYTE_0"; break;
1197 case SdwaSel::BYTE_1: O << "BYTE_1"; break;
1198 case SdwaSel::BYTE_2: O << "BYTE_2"; break;
1199 case SdwaSel::BYTE_3: O << "BYTE_3"; break;
1200 case SdwaSel::WORD_0: O << "WORD_0"; break;
1201 case SdwaSel::WORD_1: O << "WORD_1"; break;
1202 case SdwaSel::DWORD: O << "DWORD"; break;
1209 raw_ostream &O) {
1210 O << "dst_sel:";
1211 printSDWASel(MI, OpNo, O);
1216 raw_ostream &O) {
1217 O << "src0_sel:";
1218 printSDWASel(MI, OpNo, O);
1223 raw_ostream &O) {
1224 O << "src1_sel:";
1225 printSDWASel(MI, OpNo, O);
1230 raw_ostream &O) {
1233 O << "dst_unused:";
1236 case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
1237 case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
1238 case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
1244 const MCSubtargetInfo &STI, raw_ostream &O,
1257 printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
1259 O << "off";
1264 raw_ostream &O) {
1265 printExpSrcN(MI, OpNo, STI, O, 0);
1270 raw_ostream &O) {
1271 printExpSrcN(MI, OpNo, STI, O, 1);
1276 raw_ostream &O) {
1277 printExpSrcN(MI, OpNo, STI, O, 2);
1282 raw_ostream &O) {
1283 printExpSrcN(MI, OpNo, STI, O, 3);
1288 raw_ostream &O) {
1297 O << ' ' << TgtName;
1299 O << Index;
1301 O << " invalid_target_" << Id;
1323 raw_ostream &O) {
1371 O << Name;
1374 O << ',';
1376 O << !!(Ops[I] & Mod);
1380 O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
1383 O << ']';
1388 raw_ostream &O) {
1397 O << " op_sel:[" << Index0 << ',' << Index1 << ']';
1406 O << " op_sel:[" << FI << ',' << BC << ']';
1410 printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O);
1415 raw_ostream &O) {
1416 printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O);
1421 raw_ostream &O) {
1422 printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
1427 raw_ostream &O) {
1428 printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
1433 raw_ostream &O) {
1438 O << " index_key:" << Imm;
1443 raw_ostream &O) {
1448 O << " index_key:" << Imm;
1453 raw_ostream &O) {
1457 O << "p10";
1460 O << "p20";
1463 O << "p0";
1466 O << "invalid_param_" << Imm;
1472 raw_ostream &O) {
1474 O << "attr" << Attr;
1479 raw_ostream &O) {
1481 O << '.' << "xyzw"[Chan & 0x3];
1486 raw_ostream &O) {
1491 O << formatHex(static_cast<uint64_t>(Val));
1493 O << "gpr_idx(";
1498 O << ',';
1499 O << IdSymbolic[ModeId];
1503 O << ')';
1509 raw_ostream &O) {
1510 printRegularOperand(MI, OpNo, STI, O);
1511 O << ", ";
1512 printRegularOperand(MI, OpNo + 1, STI, O);
1516 raw_ostream &O, StringRef Asm,
1521 O << Asm;
1523 O << Default;
1528 raw_ostream &O, char Asm) {
1532 O << Asm;
1537 raw_ostream &O) {
1540 O << " mul:2";
1542 O << " mul:4";
1544 O << " div:2";
1549 raw_ostream &O) {
1563 O << "sendmsg(" << MsgName;
1565 O << ", " << getMsgOpName(MsgId, OpId, STI);
1567 O << ", " << StreamId;
1570 O << ')';
1572 O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')';
1574 O << Imm16; // Unknown imm16 code.
1581 raw_ostream &O) {
1587 O << "\"";
1595 O << "0";
1597 O << "1";
1601 O << "p";
1603 O << "i";
1608 O << "\"";
1613 raw_ostream &O) {
1621 O << " offset:";
1625 O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
1627 O << ",";
1628 O << formatDec(Imm & LANE_MASK);
1631 O << ")";
1641 O << "swizzle(" << IdSymbolic[ID_SWAP];
1642 O << ",";
1643 O << formatDec(XorMask);
1644 O << ")";
1649 O << "swizzle(" << IdSymbolic[ID_REVERSE];
1650 O << ",";
1651 O << formatDec(XorMask + 1);
1652 O << ")";
1662 O << "swizzle(" << IdSymbolic[ID_BROADCAST];
1663 O << ",";
1664 O << formatDec(GroupSize);
1665 O << ",";
1666 O << formatDec(OrMask);
1667 O << ")";
1670 O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1671 O << ",";
1672 printSwizzleBitmask(AndMask, OrMask, XorMask, O);
1673 O << ")";
1677 printU16ImmDecOperand(MI, OpNo, O);
1683 raw_ostream &O) {
1698 O << "vmcnt(" << Vmcnt << ')';
1704 O << ' ';
1705 O << "expcnt(" << Expcnt << ')';
1711 O << ' ';
1712 O << "lgkmcnt(" << Lgkmcnt << ')';
1718 raw_ostream &O) {
1733 O << ' ';
1734 O << Name << '(' << Val << ')';
1739 O << formatHex(Imm16);
1745 raw_ostream &O) {
1763 O << Prefix << "instid0(" << Name << ')';
1771 O << Prefix << "instskip(" << Name << ')';
1778 O << Prefix << "instid1(" << Name << ')';
1783 O << "0";
1787 const MCSubtargetInfo &STI, raw_ostream &O) {
1793 O << "hwreg(";
1795 O << HwRegName;
1797 O << Id;
1800 O << ", " << Offset << ", " << Width;
1801 O << ')';
1806 raw_ostream &O) {
1812 O << ' ' << formatDec(Imm);
1817 raw_ostream &O) {
1822 O << " byte_sel:" << formatDec(Imm);