Lines Matching defs:MI
43 void AMDGPUInstPrinter::printInst(const MCInst *MI, uint64_t Address,
46 printInstruction(MI, Address, STI, OS);
50 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
53 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
56 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
59 const MCOperand &Op = MI->getOperand(OpNo);
71 printU32ImmOperand(MI, OpNo, STI, O);
74 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
76 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
79 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
81 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
84 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
86 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
89 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
92 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
95 void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
97 if (MI->getOperand(OpNo).getImm()) {
102 void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
105 uint32_t Imm = MI->getOperand(OpNo).getImm();
110 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
115 printU16ImmDecOperand(MI, OpNo, O);
119 void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
122 uint32_t Imm = MI->getOperand(OpNo).getImm();
126 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
134 printU16ImmDecOperand(MI, OpNo, O);
138 void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
141 if (MI->getOperand(OpNo).getImm()) {
143 printU8ImmDecOperand(MI, OpNo, O);
147 void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
150 if (MI->getOperand(OpNo).getImm()) {
152 printU8ImmDecOperand(MI, OpNo, O);
156 void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
159 printU32ImmOperand(MI, OpNo, STI, O);
162 void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
165 O << formatHex(MI->getOperand(OpNo).getImm());
168 void AMDGPUInstPrinter::printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
172 printSMEMOffset(MI, OpNo, STI, O);
175 void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
178 printU32ImmOperand(MI, OpNo, STI, O);
181 void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
183 auto Imm = MI->getOperand(OpNo).getImm();
189 printTH(MI, TH, Scope, O);
197 !(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD)) ? " sc0"
209 void AMDGPUInstPrinter::printTH(const MCInst *MI, int64_t TH, int64_t Scope,
215 const unsigned Opcode = MI->getOpcode();
292 void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
294 if (MI->getOperand(OpNo).getImm()) {
296 printU16ImmOperand(MI, OpNo, STI, O);
300 void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
302 unsigned Dim = MI->getOperand(OpNo).getImm();
312 void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
315 printNamedBit(MI, OpNo, O, "a16");
317 printNamedBit(MI, OpNo, O, "r128");
320 void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
325 void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
331 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format);
334 unsigned Val = MI->getOperand(OpNo).getImm();
385 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
387 auto Opcode = MI->getOpcode();
405 printRegularOperand(MI, OpNo, STI, O);
446 void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
453 printRegularOperand(MI, OpNo, STI, O);
679 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
682 unsigned Imm = MI->getOperand(OpNo).getImm();
687 switch (MI->getOpcode()) {
701 void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
704 unsigned Imm = MI->getOperand(OpNo).getImm();
711 void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
714 unsigned Imm = MI->getOperand(OpNo).getImm();
734 void AMDGPUInstPrinter::printWaitVDST(const MCInst *MI, unsigned OpNo,
738 printU4ImmDecOperand(MI, OpNo, O);
741 void AMDGPUInstPrinter::printWaitVAVDst(const MCInst *MI, unsigned OpNo,
745 printU4ImmDecOperand(MI, OpNo, O);
748 void AMDGPUInstPrinter::printWaitVMVSrc(const MCInst *MI, unsigned OpNo,
752 printU4ImmDecOperand(MI, OpNo, O);
755 void AMDGPUInstPrinter::printWaitEXP(const MCInst *MI, unsigned OpNo,
759 printU4ImmDecOperand(MI, OpNo, O);
772 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
775 unsigned Opc = MI->getOpcode();
788 printRegularOperand(MI, OpNo, STI, O);
792 void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
795 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
797 if (OpNo >= MI->getNumOperands()) {
802 const MCOperand &Op = MI->getOperand(OpNo);
894 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
912 switch (MI->getOpcode()) {
952 if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
960 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
963 printSymbolicFormat(MI, STI, O);
967 void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
971 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
975 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
983 if (OpNo + 1 < MI->getNumOperands() &&
985 const MCOperand &Op = MI->getOperand(OpNo + 1);
997 printRegularOperand(MI, OpNo + 1, STI, O);
1006 switch (MI->getOpcode()) {
1014 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::src1))
1020 void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
1024 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
1028 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
1031 printRegularOperand(MI, OpNo + 1, STI, O);
1036 switch (MI->getOpcode()) {
1042 if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1049 void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
1055 unsigned Imm = MI->getOperand(OpNo).getImm();
1063 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
1068 unsigned Imm = MI->getOperand(OpNo).getImm();
1069 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
1084 printU4ImmDecOperand(MI, OpNo, O);
1088 printU4ImmDecOperand(MI, OpNo, O);
1092 printU4ImmDecOperand(MI, OpNo, O);
1144 printU4ImmDecOperand(MI, OpNo, O);
1152 printU4ImmDecOperand(MI, OpNo, O);
1158 void AMDGPUInstPrinter::printDppRowMask(const MCInst *MI, unsigned OpNo,
1162 printU4ImmOperand(MI, OpNo, STI, O);
1165 void AMDGPUInstPrinter::printDppBankMask(const MCInst *MI, unsigned OpNo,
1169 printU4ImmOperand(MI, OpNo, STI, O);
1172 void AMDGPUInstPrinter::printDppBoundCtrl(const MCInst *MI, unsigned OpNo,
1175 unsigned Imm = MI->getOperand(OpNo).getImm();
1181 void AMDGPUInstPrinter::printDppFI(const MCInst *MI, unsigned OpNo,
1184 unsigned Imm = MI->getOperand(OpNo).getImm();
1190 void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
1194 unsigned Imm = MI->getOperand(OpNo).getImm();
1207 void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
1211 printSDWASel(MI, OpNo, O);
1214 void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
1218 printSDWASel(MI, OpNo, O);
1221 void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
1225 printSDWASel(MI, OpNo, O);
1228 void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
1234 unsigned Imm = MI->getOperand(OpNo).getImm();
1243 void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
1246 unsigned Opc = MI->getOpcode();
1248 unsigned En = MI->getOperand(EnIdx).getImm();
1253 if (MI->getOperand(ComprIdx).getImm())
1257 printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
1262 void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
1265 printExpSrcN(MI, OpNo, STI, O, 0);
1268 void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
1271 printExpSrcN(MI, OpNo, STI, O, 1);
1274 void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
1277 printExpSrcN(MI, OpNo, STI, O, 2);
1280 void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
1283 printExpSrcN(MI, OpNo, STI, O, 3);
1286 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
1292 unsigned Id = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1320 void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
1324 unsigned Opc = MI->getOpcode();
1340 (ModIdx != -1) ? MI->getOperand(ModIdx).getImm() : DefaultValue;
1345 if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsSWMMAC ||
1346 MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsWMMA) {
1354 Ops[NumOps++] = MI->getOperand(Idx).getImm();
1363 MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
1366 MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
1386 void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1389 unsigned Opc = MI->getOpcode();
1393 unsigned Mod = MI->getOperand(SrcMod).getImm();
1403 unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
1404 unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0);
1410 printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O);
1413 void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1416 printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O);
1419 void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1422 printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
1425 void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1428 printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
1431 void AMDGPUInstPrinter::printIndexKey8bit(const MCInst *MI, unsigned OpNo,
1434 auto Imm = MI->getOperand(OpNo).getImm() & 0x7;
1441 void AMDGPUInstPrinter::printIndexKey16bit(const MCInst *MI, unsigned OpNo,
1444 auto Imm = MI->getOperand(OpNo).getImm() & 0x7;
1451 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1454 unsigned Imm = MI->getOperand(OpNum).getImm();
1470 void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1473 unsigned Attr = MI->getOperand(OpNum).getImm();
1477 void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1480 unsigned Chan = MI->getOperand(OpNum).getImm();
1484 void AMDGPUInstPrinter::printGPRIdxMode(const MCInst *MI, unsigned OpNo,
1488 unsigned Val = MI->getOperand(OpNo).getImm();
1507 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1510 printRegularOperand(MI, OpNo, STI, O);
1512 printRegularOperand(MI, OpNo + 1, STI, O);
1515 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1518 const MCOperand &Op = MI->getOperand(OpNo);
1527 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1529 const MCOperand &Op = MI->getOperand(OpNo);
1535 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
1538 int Imm = MI->getOperand(OpNo).getImm();
1547 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1552 const unsigned Imm16 = MI->getOperand(OpNo).getImm();
1611 void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1616 uint16_t Imm = MI->getOperand(OpNo).getImm();
1677 printU16ImmDecOperand(MI, OpNo, O);
1681 void AMDGPUInstPrinter::printSWaitCnt(const MCInst *MI, unsigned OpNo,
1686 unsigned SImm16 = MI->getOperand(OpNo).getImm();
1716 void AMDGPUInstPrinter::printDepCtr(const MCInst *MI, unsigned OpNo,
1721 uint64_t Imm16 = MI->getOperand(OpNo).getImm() & 0xffff;
1743 void AMDGPUInstPrinter::printSDelayALU(const MCInst *MI, unsigned OpNo,
1757 unsigned SImm16 = MI->getOperand(OpNo).getImm();
1786 void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1789 unsigned Val = MI->getOperand(OpNo).getImm();
1804 void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
1807 uint16_t Imm = MI->getOperand(OpNo).getImm();
1815 void AMDGPUInstPrinter::printByteSel(const MCInst *MI, unsigned OpNo,
1818 uint8_t Imm = MI->getOperand(OpNo).getImm();