Lines Matching defs:SubReg

80     /// Register class required to hold the value stored in the SubReg.
86     unsigned SubReg = AMDGPU::NoSubRegister;
130   /// Find right-shifted by RShift amount version of the SubReg if it exists,
132   unsigned shiftSubReg(unsigned SubReg, unsigned RShift) const;
138   /// Cache for getSubReg method: {Offset, Size} -> SubReg index.
180 unsigned GCNRewritePartialRegUses::shiftSubReg(unsigned SubReg,
182   unsigned Offset = TRI->getSubRegIdxOffset(SubReg) - RShift;
183   return getSubReg(Offset, TRI->getSubRegIdxSize(SubReg));
283     for (auto [SubReg, SRI] : SubRegs)
284       // Check that all registers in MinRC support SRI.SubReg subregister.
285       assert(MinRC == TRI->getSubClassWithSubReg(MinRC, SRI.SubReg));
299   for (auto [SubReg, SRI] : SubRegs) {
300     unsigned SubRegOffset = TRI->getSubRegIdxOffset(SubReg);
301     unsigned SubRegEnd = SubRegOffset + TRI->getSubRegIdxSize(SubReg);
311       CoverSubreg = SubReg;
323   for (auto [SubReg, SRI] : SubRegs)
324     MaxAlign = std::max(MaxAlign, TRI->getSubRegAlignmentNumBits(RC, SubReg));
327   for (auto [SubReg, SRI] : SubRegs) {
328     if (TRI->getSubRegAlignmentNumBits(RC, SubReg) != MaxAlign)
331         std::min(FirstMaxAlignedSubRegOffset, TRI->getSubRegIdxOffset(SubReg));
390     if (unsigned NewSubReg = I->second.SubReg)
426     const unsigned SubReg = MO.getSubReg();
427     assert(SubReg != AMDGPU::NoSubRegister); // Due to [1].
428     LLVM_DEBUG(dbgs() << "  " << TRI->getSubRegIndexName(SubReg) << ':');
430     const auto [I, Inserted] = SubRegs.try_emplace(SubReg);
434       SubRegRC = TRI->getSubRegisterClass(RC, SubReg);
469     unsigned SubReg = SubRegs[MO.getSubReg()].SubReg;
470     MO.setSubReg(SubReg);
471     if (SubReg == AMDGPU::NoSubRegister && MO.isDef())