Lines Matching +full:reg +full:- +full:init

1 //===-- GCNPreRAOptimizations.cpp -----------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
25 //===----------------------------------------------------------------------===//
36 #define DEBUG_TYPE "amdgpu-pre-ra-optimizations"
47   bool processReg(Register Reg);
59     return "AMDGPU Pre-RA optimizations";
72                       "AMDGPU Pre-RA optimizations", false, false)
74 INITIALIZE_PASS_END(GCNPreRAOptimizations, DEBUG_TYPE, "Pre-RA optimizations",
85 bool GCNPreRAOptimizations::processReg(Register Reg) {
88   uint64_t Init = 0;
91   bool IsAGPRDst = TRI->isAGPRClass(MRI->getRegClass(Reg));
93   for (MachineInstr &I : MRI->def_instructions(Reg)) {
113       bool IsAGPRSrc = TRI->isAGPRClass(MRI->getRegClass(SrcReg));
121       for (auto &Def : MRI->def_instructions(SrcReg)) {
132             // Propagate source reg of accvgpr write to this copy instruction
136             // Reg uses were changed, collect unique set of registers to update
151       if (I.getOperand(0).getReg() != Reg || !I.getOperand(1).isImm() ||
162         Init |= I.getOperand(1).getImm() & 0xffffffff;
168         Init |= static_cast<uint64_t>(I.getOperand(1).getImm()) << 32;
175   // For AGPR reg, check if live intervals need to be updated.
179         LIS->removeInterval(RegToUpdate);
180         LIS->createAndComputeVirtRegInterval(RegToUpdate);
187   // For SGPR reg, check if we can combine instructions.
188   if (!Def0 || !Def1 || Def0->getParent() != Def1->getParent())
194   if (SlotIndex::isEarlierInstr(LIS->getInstructionIndex(*Def1),
195                                 LIS->getInstructionIndex(*Def0)))
198   LIS->RemoveMachineInstrFromMaps(*Def0);
199   LIS->RemoveMachineInstrFromMaps(*Def1);
200   auto NewI = BuildMI(*Def0->getParent(), *Def0, Def0->getDebugLoc(),
201                       TII->get(AMDGPU::S_MOV_B64_IMM_PSEUDO), Reg)
202                   .addImm(Init);
204   Def0->eraseFromParent();
205   Def1->eraseFromParent();
206   LIS->InsertMachineInstrInMaps(*NewI);
207   LIS->removeInterval(Reg);
208   LIS->createAndComputeVirtRegInterval(Reg);
227   for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
228     Register Reg = Register::index2VirtReg(I);
229     if (!LIS->hasInterval(Reg))
231     const TargetRegisterClass *RC = MRI->getRegClass(Reg);
232     if ((RC->MC->getSizeInBits() != 64 || !TRI->isSGPRClass(RC)) &&
233         (ST.hasGFX90AInsts() || !TRI->isAGPRClass(RC)))
236     Changed |= processReg(Reg);