Lines Matching defs:VALU

679   // SGPR was written by a VALU instruction.
724   // SGPR was written by a VALU Instruction.
745   // Check for DPP VGPR read after VALU VGPR write and EXEC write.
775   // v_div_fmas requires 4 wait states after a write to vcc from a VALU
886 int GCNHazardRecognizer::checkVALUHazards(MachineInstr *VALU) {
889   if (ST.hasTransForwardingHazard() && !SIInstrInfo::isTRANS(*VALU)) {
892     auto IsTransDefFn = [this, VALU](const MachineInstr &MI) {
899       for (const MachineOperand &Use : VALU->explicit_uses()) {
916     auto IsShift16BitDefFn = [this, VALU](const MachineInstr &MI) {
935         for (const MachineOperand &Use : VALU->explicit_uses()) {
964     for (const MachineOperand &Use : VALU->explicit_uses()) {
978     if (VALU->readsRegister(AMDGPU::VCC, TRI)) {
986     switch (VALU->getOpcode()) {
989       MachineOperand *Src = TII.getNamedOperand(*VALU, AMDGPU::OpName::src0);
1017   for (const MachineOperand &Def : VALU->defs()) {
1441   // This makes va_vdst count unusable with a mixture of VALU and TRANS.
1512   //   Va <- VALU [PreExecPos]
1516   //   Vb <- VALU [PostExecPos]
1541     // Too many VALU states have passed
1657   //   Va <- TRANS VALU
1678     // Too many VALU states have passed
2495     // Only hazard if register is defined by a VALU and a DGEMM is found after
2541       // is a DGEMM instruction in-between a VALU and a VMEM instruction it
2773   //   1. VALU reads SGPR as mask
2836     // VALU access to any SGPR or literal constant other than HazardReg