Lines Matching defs:Use
690 for (const MachineOperand &Use : SMRD->uses()) {
691 if (!Use.isReg())
694 SmrdSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn,
707 SmrdSgprWaitStates - getWaitStatesSinceDef(Use.getReg(),
729 for (const MachineOperand &Use : VMEM->uses()) {
730 if (!Use.isReg() || TRI.isVectorRegister(MF.getRegInfo(), Use.getReg()))
734 VmemSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn,
753 for (const MachineOperand &Use : DPP->uses()) {
754 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
758 Use.getReg(),
899 for (const MachineOperand &Use : VALU->explicit_uses()) {
900 if (Use.isReg() && TRI->regsOverlap(Def, Use.getReg()))
935 for (const MachineOperand &Use : VALU->explicit_uses()) {
936 if (Use.isReg() && TRI->regsOverlap(Def, Use.getReg()))
964 for (const MachineOperand &Use : VALU->explicit_uses()) {
965 if (!Use.isReg())
968 UseReg = Use.getReg();
1134 // Use V_MOV_B32 v?, v?. Register must be alive so use src0 of V_PERMLANE*
1502 for (const MachineOperand &Use : MI->explicit_uses()) {
1503 if (Use.isReg() && TRI.isVGPR(MF.getRegInfo(), Use.getReg()))
1504 SrcVGPRs.insert(Use.getReg());
1651 for (const MachineOperand &Use : MI->explicit_uses()) {
1652 if (Use.isReg() && TRI.isVGPR(MF.getRegInfo(), Use.getReg()))
1653 SrcVGPRs.insert(Use.getReg());
1996 for (const MachineOperand &Use : MI->explicit_uses()) {
1999 if (!Use.isReg() || !TRI.isVGPR(MF.getRegInfo(), Use.getReg()))
2003 getWaitStatesSinceDef(Use.getReg(), IsVALUFn, MaxWaitStates);
2202 for (const MachineOperand &Use : MI->explicit_uses()) {
2221 if (!Use.isReg())
2223 Register Reg = Use.getReg();
2246 int OpNo = Use.getOperandNo();
2519 for (const MachineOperand &Use : MI->explicit_uses()) {
2520 if (!Use.isReg())
2522 Reg = Use.getReg();
2530 if (&Use - &MI->getOperand(0) != SrcCIdx)