Lines Matching defs:OrigMI

63   MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI,
68   MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI,
205 MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
215   auto OrigOp = OrigMI.getOpcode();
235   auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI,
236                          OrigMI.getDebugLoc(), TII->get(DPPOp))
237     .setMIFlags(OrigMI.getFlags());
242     if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) {
246     if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::sdst)) {
278     auto *Mod0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0_modifiers);
302     auto *Mod1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1_modifiers);
314     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
335     auto *Mod2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2_modifiers);
344     auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2);
357       auto *ClampOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::clamp);
361       auto *VdstInOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst_in);
366       auto *OmodOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::omod);
372       if (TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel)) {
377         if (Mod0 && TII->isVOP3(OrigMI) && !TII->isVOP3P(OrigMI))
388       if (TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel_hi)) {
405       auto *NegOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_lo);
409       auto *NegHiOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_hi);
413       auto *ByteSelOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::byte_sel);
486     MachineInstr &OrigMI, MachineInstr &MovMI, RegSubRegPair CombOldVGPR,
490     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
495     if (!isIdentityValue(OrigMI.getOpcode(), OldOpndValue)) {
507   return createDPPInst(OrigMI, MovMI, CombOldVGPR, CombBCZ, IsShrinkable);
635     auto &OrigMI = *Use->getParent();
636     LLVM_DEBUG(dbgs() << "  try: " << OrigMI);
638     auto OrigOp = OrigMI.getOpcode();
642       Register FwdReg = OrigMI.getOperand(0).getReg();
645       if (execMayBeModifiedBeforeAnyUse(*MRI, FwdReg, OrigMI)) {
651       unsigned OpNo, E = OrigMI.getNumOperands();
653         if (OrigMI.getOperand(OpNo).getReg() == DPPMovReg) {
654           FwdSubReg = OrigMI.getOperand(OpNo + 1).getImm();
666       RegSeqWithOpNos[&OrigMI].push_back(OpNo);
670     bool IsShrinkable = isShrinkable(OrigMI);
679     if (OrigMI.modifiesRegister(AMDGPU::EXEC, ST->getRegisterInfo())) {
684     auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0);
685     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
686     if (Use != Src0 && !(Use == Src1 && OrigMI.isCommutable())) { // [1]
691     auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2);
699           << "  " << OrigMI
704     LLVM_DEBUG(dbgs() << "  combining: " << OrigMI);
706       if (auto *DPPInst = createDPPInst(OrigMI, MovMI, CombOldVGPR,
712       assert(Use == Src1 && OrigMI.isCommutable()); // by check [1]
713       auto *BB = OrigMI.getParent();
714       auto *NewMI = BB->getParent()->CloneMachineInstr(&OrigMI);
715       BB->insert(OrigMI, NewMI);
730     OrigMIs.push_back(&OrigMI);