Lines Matching defs:CombOldVGPR

64                               RegSubRegPair CombOldVGPR,
69                               RegSubRegPair CombOldVGPR, bool CombBCZ,
207                                            RegSubRegPair CombOldVGPR,
258           CombOldVGPR,
262       auto *Def = getVRegSubRegDef(CombOldVGPR, *MRI);
263       DPPInst.addReg(CombOldVGPR.Reg, Def ? 0 : RegState::Undef,
264                      CombOldVGPR.SubReg);
486     MachineInstr &OrigMI, MachineInstr &MovMI, RegSubRegPair CombOldVGPR,
488   assert(CombOldVGPR.Reg);
499     CombOldVGPR = getRegSubRegPair(*Src1);
502     if (!isOfRegClass(CombOldVGPR, *RC, *MRI)) {
507   return createDPPInst(OrigMI, MovMI, CombOldVGPR, CombBCZ, IsShrinkable);
612   auto CombOldVGPR = getRegSubRegPair(*OldOpnd);
614   if (CombBCZ && OldOpndValue) { // CombOldVGPR should be undef
616     CombOldVGPR = RegSubRegPair(
619                              TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg);
706       if (auto *DPPInst = createDPPInst(OrigMI, MovMI, CombOldVGPR,
719                 createDPPInst(*NewMI, MovMI, CombOldVGPR, OldOpndValue, CombBCZ,