Lines Matching full:cpol
114 bits<5> cpol;
136 let Inst{16} = !if(ps.has_glc, cpol{CPolBit.GLC}, ps.glcValue);
137 let Inst{17} = cpol{CPolBit.SLC};
175 bits<6> cpol;
185 let Inst{54-53} = cpol{2-1}; // th{2-1}
186 let Inst{52} = !if(ps.IsAtomicRet, 1, cpol{0}); // th{0}
187 let Inst{51-50} = cpol{4-3}; // scope
214 !if(HasTiedOutput, (ins CPol:$cpol, vdata_op:$vdst_in),
215 (ins CPol_0:$cpol))),
216 " $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$cpol"> {
234 (ins flat_offset:$offset, CPol_0:$cpol)),
235 " $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$cpol"> {
257 (ins flat_offset:$offset, CPol_0:$cpol),
259 " $vdst, "#!if(EnableSaddr, "$saddr", "off")#"$offset$cpol"> {
293 (ins flat_offset:$offset, CPol_0:$cpol)),
294 " $vaddr"#!if(EnableSaddr, ", $saddr", ", off")#"$offset$cpol"> {
321 (ins flat_offset:$offset, CPol:$cpol)),
322 " $vdata, "#!if(EnableSaddr, "$saddr", "off")#"$offset$cpol"> {
340 FLAT_Pseudo<opName, (outs), (ins CPol:$cpol), "$cpol", [(node)]> {
388 !if(HasTiedOutput, (ins CPol:$cpol, getLdStRegisterOperand<regClass>.ret:$vdst_in),
389 (ins CPol_0:$cpol))),
390 " $vdst, "#!if(EnableVaddr, "$vaddr, ", "off, ")#!if(EnableSaddr, "$saddr", "off")#"$offset$cpol"> {
411 (ins vdata_op:$vdata, VGPR_32:$vaddr, SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, CPol_0:$cpol),
413 (ins vdata_op:$vdata, SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, CPol_0:$cpol),
415 (ins vdata_op:$vdata, VGPR_32:$vaddr, flat_offset:$offset, CPol_0:$cpol),
416 (ins vdata_op:$vdata, flat_offset:$offset, CPol_0:$cpol)))),
417 " "#!if(EnableVaddr, "$vaddr", "off")#", $vdata, "#!if(EnableSaddr, "$saddr", "off")#"$offset$cpol"> {
465 (ins VGPR_32:$vaddr, SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, CPol:$cpol),
467 (ins SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, CPol:$cpol),
469 (ins VGPR_32:$vaddr, flat_offset:$offset, CPol:$cpol),
470 (ins flat_offset:$offset, CPol:$cpol)))),
471 " "#!if(EnableVaddr, "$vaddr, ", "off, ")#!if(EnableSaddr, "$saddr", "off")#"$offset$cpol"> {
534 (ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_0:$cpol),
535 " $vaddr, $vdata$offset$cpol">,
551 (ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_GLC1:$cpol),
552 " $vdst, $vaddr, $vdata$offset$cpol">,
581 (ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_0:$cpol),
582 " $vaddr, $vdata, off$offset$cpol">,
590 (ins VGPR_32:$vaddr, data_op:$vdata, SReg_64:$saddr, flat_offset:$offset, CPol_0:$cpol),
591 " $vaddr, $vdata, $saddr$offset$cpol">,
612 (ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_GLC1:$cpol),
613 " $vdst, $vaddr, $vdata, off$offset$cpol">,
621 (ins VGPR_32:$vaddr, data_op:$vdata, SReg_64:$saddr, flat_offset:$offset, CPol_GLC1:$cpol),
622 " $vdst, $vaddr, $vdata, $saddr$offset$cpol">,
1830 let Inst{25} = !if(has_sccb, cpol{CPolBit.SCC}, ps.sccbValue);
1847 let Inst{25} = !if(ps.has_sccb, cpol{CPolBit.SCC}, ps.sccbValue);
2105 let Inst{12} = !if(ps.has_dlc, cpol{CPolBit.DLC}, ps.dlcValue);
2351 let Inst{13} = !if(ps.has_dlc, cpol{CPolBit.DLC}, ps.dlcValue);
2352 let Inst{14} = !if(ps.has_glc, cpol{CPolBit.GLC}, ps.glcValue);
2353 let Inst{15} = cpol{CPolBit.SLC};