Lines Matching defs:createRegOperand

169         Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm));      \
704         MI.insert(MI.begin() + VAddrIdx, createRegOperand(VAddrRCID, Bytes[i]));
785       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
1175 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
1180 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
1186   return createRegOperand(RegCl.getRegister(Val));
1236   return createRegOperand(SRegClassID, Val >> shift);
1242   return createRegOperand(AMDGPU::VGPR_16RegClassID, RegIdxInVGPR16);
1532     return createRegOperand(IsAGPR ? getAgprClassId(Width)
1596   return createRegOperand(getVgprClassId(Width), Val);
1604   case 102: return createRegOperand(FLAT_SCR_LO);
1605   case 103: return createRegOperand(FLAT_SCR_HI);
1606   case 104: return createRegOperand(XNACK_MASK_LO);
1607   case 105: return createRegOperand(XNACK_MASK_HI);
1608   case 106: return createRegOperand(VCC_LO);
1609   case 107: return createRegOperand(VCC_HI);
1610   case 108: return createRegOperand(TBA_LO);
1611   case 109: return createRegOperand(TBA_HI);
1612   case 110: return createRegOperand(TMA_LO);
1613   case 111: return createRegOperand(TMA_HI);
1615     return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0);
1617     return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL);
1618   case 126: return createRegOperand(EXEC_LO);
1619   case 127: return createRegOperand(EXEC_HI);
1620   case 235: return createRegOperand(SRC_SHARED_BASE_LO);
1621   case 236: return createRegOperand(SRC_SHARED_LIMIT_LO);
1622   case 237: return createRegOperand(SRC_PRIVATE_BASE_LO);
1623   case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO);
1624   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1625   case 251: return createRegOperand(SRC_VCCZ);
1626   case 252: return createRegOperand(SRC_EXECZ);
1627   case 253: return createRegOperand(SRC_SCC);
1628   case 254: return createRegOperand(LDS_DIRECT);
1639   case 102: return createRegOperand(FLAT_SCR);
1640   case 104: return createRegOperand(XNACK_MASK);
1641   case 106: return createRegOperand(VCC);
1642   case 108: return createRegOperand(TBA);
1643   case 110: return createRegOperand(TMA);
1646       return createRegOperand(SGPR_NULL);
1650       return createRegOperand(SGPR_NULL);
1652   case 126: return createRegOperand(EXEC);
1653   case 235: return createRegOperand(SRC_SHARED_BASE);
1654   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1655   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1656   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1657   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1658   case 251: return createRegOperand(SRC_VCCZ);
1659   case 252: return createRegOperand(SRC_EXECZ);
1660   case 253: return createRegOperand(SRC_SCC);
1679       return createRegOperand(getVgprClassId(Width),
1705     return createRegOperand(getVgprClassId(Width), Val);
1739   return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);