Lines Matching defs:addOperand
86 addOperand(MCInst &Inst, const MCOperand& Opnd) {
87 Inst.addOperand(Opnd);
116 return addOperand(Inst, MCOperand::createImm(Imm));
130 return addOperand(Inst, MCOperand::createImm(Offset));
136 return addOperand(Inst, DAsm->decodeBoolReg(Val));
143 return addOperand(Inst, DAsm->decodeSplitBarrier(Val));
149 return addOperand(Inst, DAsm->decodeDpp8FI(Val));
157 return addOperand(Inst, DAsm->DecoderName(Imm)); \
168 return addOperand( \
178 return addOperand(Inst, \
191 return addOperand(Inst, DAsm->decodeSrcOp(OpWidth, EncImm, MandatoryLiteral,
317 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
328 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
341 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
343 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16,
357 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
359 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16,
367 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
373 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val));
421 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
436 return addOperand(Inst,
452 return addOperand(Inst, DAsm->decodeVersionImm(Imm));
973 addOperand(MI, MCOperand::createImm(BaseOpcode->A16));
2421 Inst.addOperand(MCOperand::createExpr(Add));