Lines Matching defs:ImmWidth

173                      ImmWidth)                                                 \
180                                         MandatoryLiteral, ImmWidth));          \
186                                 bool MandatoryLiteral, unsigned ImmWidth,
192                                             ImmWidth, Sema));
243 // decoded into constant of size ImmWidth, should match width of immediate used
245 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
250   return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, ImmWidth,
256 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
261   return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, ImmWidth,
265 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
270   return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, true, ImmWidth,
1392 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm,
1398   // ImmWidth 0 is a default case where operand should not allow immediates.
1401   switch (ImmWidth) {
1522                                           unsigned ImmWidth,
1535   return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth,
1541                                        bool MandatoryLiteral, unsigned ImmWidth,
1563     return decodeFPImmed(ImmWidth, Val, Sema);
1668                                   unsigned ImmWidth,
1700       return decodeFPImmed(ImmWidth, SVal, Sema);