Lines Matching defs:Imm
104 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm,
111 APInt SignedOffset(18, Imm * 4, true);
116 return addOperand(Inst, MCOperand::createImm(Imm));
119 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr,
124 Offset = SignExtend64<24>(Imm);
126 Offset = Imm & 0xFFFFF;
128 Offset = SignExtend64<21>(Imm);
153 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \
157 return addOperand(Inst, DAsm->DecoderName(Imm)); \
160 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is
164 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \
166 assert(Imm < (1 << 8) && "8-bit encoding"); \
169 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \
174 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \
176 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \
185 unsigned Imm, unsigned EncImm,
189 assert(Imm < (1U << EncSize) && "Operand doesn't fit encoding!");
195 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to
198 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
200 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register,
201 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC).
202 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp.
205 static DecodeStatus decodeAV10(MCInst &Inst, unsigned Imm, uint64_t /* Addr */,
207 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm | AMDGPU::EncValues::IS_VGPR,
213 static DecodeStatus decodeSrcReg9(MCInst &Inst, unsigned Imm,
216 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, 0,
221 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers
224 static DecodeStatus decodeSrcA9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */,
226 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, 0,
230 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding
231 // Imm{9} is acc, registers only.
233 static DecodeStatus decodeSrcAV10(MCInst &Inst, unsigned Imm,
236 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm, false, 0,
247 static DecodeStatus decodeSrcRegOrImm9(MCInst &Inst, unsigned Imm,
250 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, ImmWidth,
254 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc)
258 static DecodeStatus decodeSrcRegOrImmA9(MCInst &Inst, unsigned Imm,
261 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, ImmWidth,
267 static DecodeStatus decodeSrcRegOrImmDeferred9(MCInst &Inst, unsigned Imm,
270 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, true, ImmWidth,
308 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm,
311 assert(isUInt<10>(Imm) && "10-bit encoding expected");
312 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used");
314 bool IsHi = Imm & (1 << 9);
315 unsigned RegIdx = Imm & 0xff;
321 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,
323 assert(isUInt<8>(Imm) && "8-bit encoding expected");
325 bool IsHi = Imm & (1 << 7);
326 unsigned RegIdx = Imm & 0x7f;
331 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm,
334 assert(isUInt<9>(Imm) && "9-bit encoding expected");
337 bool IsVGPR = Imm & (1 << 8);
339 bool IsHi = Imm & (1 << 7);
340 unsigned RegIdx = Imm & 0x7f;
344 Imm & 0xFF, false, 16));
347 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm,
350 assert(isUInt<10>(Imm) && "10-bit encoding expected");
353 bool IsVGPR = Imm & (1 << 8);
355 bool IsHi = Imm & (1 << 9);
356 unsigned RegIdx = Imm & 0xff;
360 Imm & 0xFF, false, 16));
363 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm,
367 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
390 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm,
395 Imm &= 511;
411 Imm |= 512;
418 Imm |= 512;
421 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
425 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm,
428 return decodeAVLdSt(Inst, Imm, Opw, Decoder);
431 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm,
434 assert(Imm < (1 << 9) && "9-bit encoding");
437 DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64,
448 static DecodeStatus decodeVersionImm(MCInst &Inst, unsigned Imm,
452 return addOperand(Inst, DAsm->decodeVersionImm(Imm));
1277 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
1280 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
1281 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
1282 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
1283 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
1287 static int64_t getInlineImmVal32(unsigned Imm) {
1288 switch (Imm) {
1312 static int64_t getInlineImmVal64(unsigned Imm) {
1313 switch (Imm) {
1337 static int64_t getInlineImmValF16(unsigned Imm) {
1338 switch (Imm) {
1362 static int64_t getInlineImmValBF16(unsigned Imm) {
1363 switch (Imm) {
1387 static int64_t getInlineImmVal16(unsigned Imm, AMDGPU::OperandSemantics Sema) {
1388 return (Sema == AMDGPU::OperandSemantics::BF16) ? getInlineImmValBF16(Imm)
1389 : getInlineImmValF16(Imm);
1392 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm,
1394 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN &&
1395 Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
1399 // Imm value is still decoded into 32 bit immediate operand, inst printer will
1404 return MCOperand::createImm(getInlineImmVal32(Imm));
1406 return MCOperand::createImm(getInlineImmVal64(Imm));
1408 return MCOperand::createImm(getInlineImmVal16(Imm, Sema));
1758 MCOperand AMDGPUDisassembler::decodeVersionImm(unsigned Imm) const {
1765 auto [Version, W64, W32, MDP] = Encoding::decode(Imm);
1768 if (Encoding::encode(Version, W64, W32, MDP) != Imm)
1769 return MCOperand::createImm(Imm);