Lines Matching defs:Decoder
106 const MCDisassembler *Decoder) {
107 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
120 const MCDisassembler *Decoder) {
121 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
134 const MCDisassembler *Decoder) {
135 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
141 const MCDisassembler *Decoder) {
142 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
147 const MCDisassembler *Decoder) {
148 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
155 const MCDisassembler *Decoder) { \
156 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
160 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is
165 const MCDisassembler *Decoder) { \
167 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
175 const MCDisassembler *Decoder) { \
177 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
188 const MCDisassembler *Decoder) {
190 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
195 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to
200 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register,
206 const MCDisassembler *Decoder) {
208 false, 0, AMDGPU::OperandSemantics::INT, Decoder);
211 // Decoder for Src(9-bit encoding) registers only.
215 const MCDisassembler *Decoder) {
217 AMDGPU::OperandSemantics::INT, Decoder);
220 // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set
225 const MCDisassembler *Decoder) {
227 AMDGPU::OperandSemantics::INT, Decoder);
230 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding
235 const MCDisassembler *Decoder) {
237 AMDGPU::OperandSemantics::INT, Decoder);
240 // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be
249 const MCDisassembler *Decoder) {
251 (AMDGPU::OperandSemantics)OperandSemantics, Decoder);
254 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc)
260 const MCDisassembler *Decoder) {
262 (AMDGPU::OperandSemantics)OperandSemantics, Decoder);
269 const MCDisassembler *Decoder) {
271 (AMDGPU::OperandSemantics)OperandSemantics, Decoder);
310 const MCDisassembler *Decoder) {
316 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
322 const MCDisassembler *Decoder) {
327 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
333 const MCDisassembler *Decoder) {
336 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
349 const MCDisassembler *Decoder) {
352 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
365 const MCDisassembler *Decoder) {
366 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
371 uint64_t Addr, const void *Decoder) {
372 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
392 const MCDisassembler *Decoder) {
393 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
427 const MCDisassembler *Decoder) {
428 return decodeAVLdSt(Inst, Imm, Opw, Decoder);
433 const MCDisassembler *Decoder) {
435 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
450 const MCDisassembler *Decoder) {
451 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);