Lines Matching defs:DAsm

107   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
114   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0))
121   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
123   if (DAsm->isGFX12Plus()) { // GFX12 supports 24-bit signed offsets.
125   } else if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets.
135   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
136   return addOperand(Inst, DAsm->decodeBoolReg(Val));
142   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
143   return addOperand(Inst, DAsm->decodeSplitBarrier(Val));
148   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
149   return addOperand(Inst, DAsm->decodeDpp8FI(Val));
156     auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
157     return addOperand(Inst, DAsm->DecoderName(Imm));                           \
167     auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
169         Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm));      \
177     auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
179                       DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm,   \
190   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
191   return addOperand(Inst, DAsm->decodeSrcOp(OpWidth, EncImm, MandatoryLiteral,
316   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
317   return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
327   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
328   return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
336   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
341     return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
343   return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16,
352   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
357     return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
359   return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16,
366   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
367   return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
372   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
373   return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val));
393   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
394   if (!DAsm->isGFX90A()) {
403     uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags;
406     const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo();
421   return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
435   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
437                     DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64,
451   auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
452   return addOperand(Inst, DAsm->decodeVersionImm(Imm));