Lines Matching +full:abs +full:- +full:flat
1 //===- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
55 //===----------------------------------------------------------------------===//
57 //===----------------------------------------------------------------------===//
77 bool Abs = false;
82 bool hasFPModifiers() const { return Abs || Neg; }
88 Operand |= Abs ? SISrcMods::ABS : 0u;
464 // TODO: Find out how SALU supports extension of 32-bit literals to 64 bits.
1066 // clang-format off
1130 // clang-format on
1159 Op->Imm.Val = Val;
1160 Op->Imm.IsFPImm = IsFPImm;
1161 Op->Imm.Kind = ImmKindTyNone;
1162 Op->Imm.Type = Type;
1163 Op->Imm.Mods = Modifiers();
1164 Op->StartLoc = Loc;
1165 Op->EndLoc = Loc;
1173 Res->Tok.Data = Str.data();
1174 Res->Tok.Length = Str.size();
1175 Res->StartLoc = Loc;
1176 Res->EndLoc = Loc;
1184 Op->Reg.RegNo = RegNo;
1185 Op->Reg.Mods = Modifiers();
1186 Op->StartLoc = S;
1187 Op->EndLoc = E;
1194 Op->Expr = Expr;
1195 Op->StartLoc = S;
1196 Op->EndLoc = S;
1202 OS << "abs:" << Mods.Abs << " neg: " << Mods.Neg << " sext:" << Mods.Sext;
1206 //===----------------------------------------------------------------------===//
1208 //===----------------------------------------------------------------------===//
1214 int SgprIndexUnusedMin = -1;
1215 int VgprIndexUnusedMin = -1;
1216 int AgprIndexUnusedMin = -1;
1225 Ctx->getOrCreateSymbol(Twine(".kernel.sgpr_count"));
1226 Sym->setVariableValue(MCConstantExpr::create(SgprIndexUnusedMin, *Ctx));
1236 Ctx->getOrCreateSymbol(Twine(".kernel.vgpr_count"));
1239 Sym->setVariableValue(MCConstantExpr::create(totalVGPR, *Ctx));
1253 Ctx->getOrCreateSymbol(Twine(".kernel.agpr_count"));
1254 Sym->setVariableValue(MCConstantExpr::create(AgprIndexUnusedMin, *Ctx));
1258 Ctx->getOrCreateSymbol(Twine(".kernel.vgpr_count"));
1261 vSym->setVariableValue(MCConstantExpr::create(totalVGPR, *Ctx));
1271 MSTI = Ctx->getSubtargetInfo();
1273 usesSgprAt(SgprIndexUnusedMin = -1);
1274 usesVgprAt(VgprIndexUnusedMin = -1);
1276 usesAgprAt(AgprIndexUnusedMin = -1);
1284 usesSgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);
1287 usesAgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);
1290 usesVgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);
1306 /// @name Auto-generated Match Functions
1320 /// registers, and user-specified NextFreeXGPR values.
1406 copySTI().ToggleFeature("southern-islands");
1555 return const_cast<AMDGPUAsmParser*>(this)->getContext().getRegisterInfo();
1704 return Error(Parser, "only " + Twine(Width) + "-bit values are legal");
1919 // When floating-point immediate is used as operand of type i16, the 32-bit
1969 //===----------------------------------------------------------------------===//
1971 //===----------------------------------------------------------------------===//
2010 // shared_base with both 32-bit and 64-bit operands.
2012 // 32-bit operands only.
2028 if (type == MVT::f64 || type == MVT::i64) { // Expected 64-bit operand
2030 AsmParser->hasInv2PiInlineImm());
2041 llvm_unreachable("unknown 16-bit type");
2055 // We need to use 32-bit representation here because when a floating-point
2056 // inline constant is used as an i16 operand, its 32-bit representation
2057 // representation will be used. We will need the 32-bit value to check if
2061 AsmParser->hasInv2PiInlineImm());
2067 AsmParser->hasInv2PiInlineImm());
2071 if (type == MVT::f64 || type == MVT::i64) { // Expected 64-bit operand
2073 AsmParser->hasInv2PiInlineImm());
2083 type, AsmParser->hasInv2PiInlineImm());
2088 AsmParser->hasInv2PiInlineImm());
2111 // FIXME: 64-bit operands can zero extend, sign extend, or pad zeroes for FP
2117 if (type == MVT::f64) { // Expected 64-bit fp operand
2118 // We would set low 64-bits of literal to zeroes but we accept this literals
2122 if (type == MVT::i64) { // Expected 64-bit int operand
2123 // We don't allow fp literals in 64-bit integer instructions. It is
2133 // single-precision float. This is pretty odd, but it matches SP3 and what
2145 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg());
2150 // GFX90A allows DPP on 64-bit operands.
2152 AsmParser->getFeatureBits()[AMDGPU::FeatureDPALU_DPP]);
2161 if (AsmParser->isVI())
2163 if (AsmParser->isGFX9Plus())
2185 auto FB = AsmParser->getFeatureBits();
2195 const uint64_t FpSignMask = (1ULL << (Size * 8 - 1));
2197 if (Imm.Mods.Abs) {
2213 if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()),
2226 const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode());
2248 AsmParser->hasInv2PiInlineImm())) {
2254 // Non-inlineable
2255 if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand
2258 const_cast<AMDGPUAsmParser *>(AsmParser)->Warning(Inst.getLoc(),
2259 "Can't encode literal as exact 64-bit floating-point operand. "
2260 "Low 32-bits will be set to zero");
2269 // We don't allow fp literals in 64-bit integer instructions. It is
2272 llvm_unreachable("fp literal in 64-bit integer instruction.");
2281 if (AsmParser->hasInv2PiInlineImm() && Literal == 0x3fc45f306725feed) {
2363 AsmParser->hasInv2PiInlineImm())) {
2378 if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
2411 AsmParser->hasInv2PiInlineImm())) {
2427 AsmParser->hasInv2PiInlineImm())) {
2448 AsmParser->hasInv2PiInlineImm()));
2458 AsmParser->hasInv2PiInlineImm()));
2478 Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI())));
2485 //===----------------------------------------------------------------------===//
2487 //===----------------------------------------------------------------------===//
2490 // TODO: make those pre-defined variables read-only.
2491 // Currently there is none suitable machinery in the core llvm-mc for this.
2496 Sym->setVariableValue(MCConstantExpr::create(Val, Ctx));
2502 default: return -1;
2534 default: return -1;
2548 default: return -1;
2578 default: return -1;
2609 return -1;
2660 assert(R->isReg());
2661 RegNo = R->getReg();
2662 StartLoc = R->getStartLoc();
2663 EndLoc = R->getEndLoc();
2783 StringRef RegName = Reg->Name;
2827 if (RCID == -1) {
2833 const MCRegisterClass RC = TRI->getRegClass(RCID);
2842 Reg = TRI->getSubReg(Reg, SubReg);
2890 RegWidth = 32 * ((RegHi - RegLo) + 1);
2925 RegKind = RI->Kind;
2926 StringRef RegSuffix = RegName.substr(RI->Name.size());
2938 // Single 32-bit register: vXX.
2970 Error(Loc, "expected a single 32-bit register");
2985 Error(Loc, "expected a single 32-bit register");
3072 Sym->setVariableValue(MCConstantExpr::create(0, getContext()));
3087 int64_t NewMax = DwordRegIndex + divideCeil(RegWidth, 32) - 1;
3090 if (!Sym->isVariable())
3093 if (!Sym->getVariableValue(false)->evaluateAsAbsolute(OldCount))
3099 Sym->setVariableValue(MCConstantExpr::create(NewMax + 1, getContext()));
3160 // Floating-point expressions are not supported.
3161 // Can only allow floating-point literals with an
3189 // as arguments of SP3 'abs' modifier, for example:
3191 // |-1|
3203 if (Expr->evaluateAsAbsolute(IntVal)) {
3224 assert(R->isReg());
3245 return str == "abs" || str == "neg" || str == "sext";
3270 // abs(...)
3273 // -reg
3274 // -|...|
3275 // -abs(...)
3293 // 1. Before a register, e.g. "-v0", "-v[...]" or "-[v0,v1]".
3294 // 2. Before an 'abs' modifier: -abs(...)
3295 // 3. Before an SP3 'abs' modifier: -|...|
3297 // In all other cases "-" is handled as a part
3300 // Note: When "-" is followed by an integer literal,
3302 // than a floating-point NEG modifier applied to N.
3303 // Beside being contr-intuitive, such use of floating-point
3307 // v_exp_f32_e32 v5, -1 // VOP1: src0 = 0xFFFFFFFF
3308 // v_exp_f32_e64 v5, -1 // VOP3: src0 = 0x80000001
3309 // Negative fp literals with preceding "-" are
3321 isId(NextToken[0], "abs"))) {
3333 bool Abs, SP3Abs;
3337 // Disable ambiguous constructs like '--1' etc. Should use neg(-1) instead.
3350 Abs = trySkipId("abs");
3351 if (Abs && !skipToken(AsmToken::LParen, "expected left paren after abs"))
3360 if (Abs && SP3Abs)
3370 return (SP3Neg || Neg || SP3Abs || Abs || Lit) ? ParseStatus::Failure : Res;
3372 if (Lit && !Operands.back()->isImm())
3377 if (Abs && !skipToken(AsmToken::RParen, "expected closing parentheses"))
3385 Mods.Abs = Abs || SP3Abs;
3626 // 64-bit shift instructions can use only one scalar value input
3658 AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::imm) : -1;
3663 : -1;
3695 // count as using the constant bus twice - but in this case it is allowed since
3743 if (OpIdx == -1)
3814 // On GFX12 if both OpX and OpY are V_MOV_B32 then OPY uses SRC2 source-cache.
3833 auto CompSrcIdx = CompOprIdx - VOPD::Component::DST_NUM;
3848 assert(ClampIdx != -1);
3871 if (VDataIdx == -1 && isGFX10Plus()) // no return image_sample
3874 if ((DMaskIdx == -1 || TFEIdx == -1) && isGFX10_AEncoding()) // intersect_ray
3878 unsigned TFESize = (TFEIdx != -1 && Inst.getOperand(TFEIdx).getImm()) ? 1 : 0;
3917 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
3925 assert(VAddr0Idx != -1);
3926 assert(SrsrcIdx != -1);
3929 bool IsA16 = (A16Idx != -1 && Inst.getOperand(A16Idx).getImm());
3930 if (BaseOpcode->BVH) {
3931 if (IsA16 == BaseOpcode->A16)
3939 bool IsNSA = SrsrcIdx - VAddr0Idx > 1;
3941 IsNSA ? SrsrcIdx - VAddr0Idx
3951 int VAddrLastIdx = SrsrcIdx - 1;
3955 ActualAddrSize = VAddrLastIdx - VAddr0Idx + VAddrLastSize;
4023 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
4025 if (!BaseOpcode->MSAA)
4029 assert(DimIdx != -1);
4034 return DimInfo->MSAA;
4062 assert(Src0Idx != -1);
4089 assert(Src0Idx != -1);
4116 if (Src2Idx == -1)
4137 if (Src2Idx == -1)
4150 if (TRI->getRegClass(Desc.operands()[0].RegClass).getSizeInBits() <= 128)
4153 if (TRI->regsOverlap(Src2Reg, DstReg)) {
4182 SISrcMods::ABS) {
4344 // with 9-bit operands only. Ignore encodings which do not accept these.
4351 if (SrcIdx == -1)
4383 if (OpNum == -1)
4387 if ((TSFlags & SIInstrFlags::FLAT))
4399 Twine("expected a ") + Twine(OffsetSize) + "-bit signed offset");
4406 Twine("expected a ") + Twine(OffsetSize) + "-bit unsigned offset");
4416 if ((TSFlags & SIInstrFlags::FLAT) == 0)
4421 assert(OpNum != -1);
4426 "flat offset modifier is not supported on this GPU");
4430 // For pre-GFX12 FLAT instructions the offset must be positive;
4439 (AllowNegative ? Twine(OffsetSize) + "-bit signed offset"
4440 : Twine(OffsetSize - 1) + "-bit unsigned offset"));
4468 if (OpNum == -1)
4482 isGFX12Plus() ? "expected a 24-bit signed offset"
4483 : (isVI() || IsBuffer) ? "expected a 20-bit unsigned offset"
4484 : "expected a 21-bit signed offset");
4505 if (OpIdx == -1) break;
4539 if (OpSelIdx != -1) {
4544 if (OpSelHiIdx != -1) {
4545 if (Inst.getOperand(OpSelHiIdx).getImm() != -1)
4577 if (NegIdx == -1)
4654 bool HasMandatoryLiteral = getNamedOperandIdx(Opcode, OpName::imm) != -1;
4666 if (OpIdx == -1)
4715 // Returns -1 if not a register, 0 if VGPR and 1 if AGPR.
4720 return -1;
4724 return -1;
4726 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
4728 const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);
4734 if ((TSFlags & (SIInstrFlags::FLAT | SIInstrFlags::MUBUF |
4768 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);
4769 const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);
4775 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
4779 if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1))
4781 if (AGPR32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1))
4801 if (BlgpIdx == -1)
4859 // Only validate GDS for non-GWS instructions.
4888 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);
4891 assert(Data0Pos != -1);
4893 auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0);
4908 if (CPolPos == -1)
4932 SIInstrFlags::FLAT;
4983 (TID.TSFlags & (SIInstrFlags::FLAT | SIInstrFlags::MUBUF)) &&
5025 if (!Operand->isReg())
5027 unsigned Reg = Operand->getReg();
5162 Error(IDLoc, "ABS not allowed in VOP3B instructions");
5252 const auto &PrevOp = ((AMDGPUOperand &)*Operands[InvalidOprIdx - 1]);
5328 int64_t Tmp = -1;
5349 if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective)
5354 Twine(getTargetStreamer().getTargetID()->toString())).str());
5383 if (NumSGPRs->evaluateAsAbsolute(EvaluatedSGPRs) && Version.Major >= 8 &&
5392 if (NumSGPRs->evaluateAsAbsolute(EvaluatedSGPRs) &&
5403 // (alignTo(max(1u, NumGPR), GPREncodingGranule) / GPREncodingGranule) - 1
5405 unsigned Granule) -> const MCExpr * {
5491 if ((EvaluatableExpr = ExprVal->evaluateAsAbsolute(IVal))) {
5531 "directive is not supported with architected flat scratch",
5593 "directive is not supported with architected flat scratch",
5623 "directive is not supported with architected flat scratch",
5632 "directive is not supported without architected flat scratch",
5676 "directive is not supported with architected flat scratch",
5686 if (Val != getTargetStreamer().getTargetID()->isXnackOnOrAny())
5807 getTargetStreamer().getTargetID()->isXnackOnOrAny(),
5815 VGPRBlocks->evaluateAsAbsolute(EvaluatedVGPRBlocks);
5827 if (SGPRBlocks->evaluateAsAbsolute(EvaluatedSGPRBlocks) &&
5851 if (!KD.kernarg_size->evaluateAsAbsolute(IVal))
5863 bool AccumEvaluatable = AccumOffset->evaluateAsAbsolute(EvaluatedAccum);
5871 if (NextFreeVGPR->evaluateAsAbsolute(EvaluatedNumVGPR) &&
6001 ".amd_amdgpu_isa directive is not available on non-amdgcn "
6006 if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective)
6052 << getContext().getAsmInfo()->getSeparatorString();
6068 /// Parse the assembler directive for new MsgPack-format PAL metadata.
6076 if (!PALMetadata->setFromString(String))
6081 /// Parse the assembler directive for old linear-format PAL metadata.
6086 "not available on non-amdpal OSes")).str());
6090 PALMetadata->setLegacy();
6105 PALMetadata->setRegister(Key, Value);
6134 return Error(SizeLoc, "size must be non-negative");
6148 // to make sure the alignment fits nicely into a 32-bit integer.
6156 Symbol->redefineIfPossible();
6157 if (!Symbol->isUndefined())
6190 "not available on non-amdhsa OSes"))
6242 return (isVI() || isGFX9()) && getTargetStreamer().getTargetID()->isXnackSupported();
6254 // On GFX10Plus flat scratch is not a valid register operand and can only be
6315 if (Operands.size() - Prefix > 1) {
6336 return Name.substr(0, Name.size() - 8);
6340 return Name.substr(0, Name.size() - 4);
6344 return Name.substr(0, Name.size() - 4);
6348 return Name.substr(0, Name.size() - 4);
6352 return Name.substr(0, Name.size() - 5);
6402 //===----------------------------------------------------------------------===//
6404 //===----------------------------------------------------------------------===//
6699 unsigned Idx = i->second;
6717 //===----------------------------------------------------------------------===//
6719 //===----------------------------------------------------------------------===//
6972 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands[Size - 2]);
7012 //===----------------------------------------------------------------------===//
7014 //===----------------------------------------------------------------------===//
7077 //===----------------------------------------------------------------------===//
7079 //===----------------------------------------------------------------------===//
7095 IntVal = encode(ISA, IntVal, -1);
7205 .Default(-1);
7221 .Default(-1);
7257 //===----------------------------------------------------------------------===//
7259 //===----------------------------------------------------------------------===//
7342 //===----------------------------------------------------------------------===//
7344 //===----------------------------------------------------------------------===//
7399 if (!isUIntN(Width, Val - 1))
7423 return Error(Loc, "invalid immediate: only 16-bit values are legal");
7433 //===----------------------------------------------------------------------===//
7435 //===----------------------------------------------------------------------===//
7541 return Error(Loc, "invalid immediate: only 16-bit values are legal");
7554 //===----------------------------------------------------------------------===//
7556 //===----------------------------------------------------------------------===//
7569 .Default(-1);
7571 if (Slot == -1)
7595 .Default(-1);
7596 if (AttrChan == -1)
7617 //===----------------------------------------------------------------------===//
7619 //===----------------------------------------------------------------------===//
7641 //===----------------------------------------------------------------------===//
7643 //===----------------------------------------------------------------------===//
7722 if (Expr->evaluateAsAbsolute(Imm))
7743 if (Expr->evaluateAsAbsolute(IntVal)) {
7820 for (unsigned i = Operands.size() - 1; i > 0; --i) {
7888 find_if(Fields, [Id](StructuredOpField *F) { return F->Id == Id; });
7891 if ((*I)->IsDefined)
7895 (*I)->Loc = getLoc();
7896 if (!parseExpr((*I)->Val))
7898 (*I)->IsDefined = true;
7908 return F->validate(*this);
7912 //===----------------------------------------------------------------------===//
7914 //===----------------------------------------------------------------------===//
7970 "expected a 2-bit lane id")) {
7999 0, GroupSize - 1,
8000 "lane id must be in the interval [0,group size - 1]",
8002 Imm = encodeBitmaskPerm(BITMASK_MAX - GroupSize + 1, LaneIdx, 0);
8026 Imm = encodeBitmaskPerm(BITMASK_MAX, 0, GroupSize - 1);
8066 Error(StrLoc, "expected a 5-character mask");
8075 unsigned Mask = 1 << (BITMASK_WIDTH - 1 - i);
8108 Error(OffsetLoc, "expected a 16-bit offset");
8170 //===----------------------------------------------------------------------===//
8172 //===----------------------------------------------------------------------===//
8233 return Error(S, "invalid immediate: only 4-bit values are legal");
8245 //===----------------------------------------------------------------------===//
8247 //===----------------------------------------------------------------------===//
8260 AMDGPUOperand &Opr = ((AMDGPUOperand &)*Operands[Operands.size() - 1]);
8269 Error(Loc, "expected a 16-bit signed jump offset");
8275 //===----------------------------------------------------------------------===//
8277 //===----------------------------------------------------------------------===//
8283 //===----------------------------------------------------------------------===//
8285 //===----------------------------------------------------------------------===//
8319 // Handle tokens like 'offen' which are sometimes hard-coded into the
8334 //===----------------------------------------------------------------------===//
8336 //===----------------------------------------------------------------------===//
8348 // 32-bit literals are only supported on CI and we only want to use them
8349 // when the offset is > 8-bits.
8353 //===----------------------------------------------------------------------===//
8355 //===----------------------------------------------------------------------===//
8379 // For pre-gfx11 targets, both bound_ctrl:0 and bound_ctrl:1 are encoded as 1.
8481 if (OpSelIdx == -1)
8496 if (DstIdx == -1)
8532 && Desc.operands()[OpNum + 1].RegClass != -1
8535 MCOI::OperandConstraint::TIED_TO) == -1;
8601 if (OpSelIdx != -1)
8606 if (OpSelIdx == -1)
8620 if (OpIdx == -1)
8727 if (OpSelIdx != -1) {
8732 if (OpSelHiIdx != -1) {
8733 int DefaultVal = IsPacked ? -1 : 0;
8739 if (NegLoIdx != -1)
8743 if (NegHiIdx != -1)
8758 if (OpSelIdx != -1)
8761 if (OpSelHiIdx != -1)
8764 if (NegLoIdx != -1)
8767 if (NegHiIdx != -1)
8772 if (OpIdx == -1)
8777 if (ModIdx == -1)
8784 ->getRegClass(AMDGPU::VGPR_16RegClassID)
8815 if (AMDGPU::getNamedOperandIdx(Opc, OpName) != -1)
8850 //===----------------------------------------------------------------------===//
8852 //===----------------------------------------------------------------------===//
8908 //===----------------------------------------------------------------------===//
8910 //===----------------------------------------------------------------------===//
8940 //===----------------------------------------------------------------------===//
8942 //===----------------------------------------------------------------------===//
8956 //===----------------------------------------------------------------------===//
8958 //===----------------------------------------------------------------------===//
8985 Encoding = DimInfo->Encoding;
9008 //===----------------------------------------------------------------------===//
9010 //===----------------------------------------------------------------------===//
9033 return Error(Loc, "expected a 3-bit value");
9077 return -1;
9082 return -1;
9087 return -1;
9089 Error(Loc, "expected a 2-bit value");
9090 return -1;
9097 return -1;
9112 return -1;
9131 .Default({-1, 0, 0});
9134 if (Check.Ctrl == -1) {
9144 return -1;
9158 int64_t Val = -1;
9177 if (Val == -1)
9197 bool IsMAC = OldIdx != -1 && Src2ModIdx != -1 &&
9198 Desc.getOperandConstraint(OldIdx, MCOI::TIED_TO) == -1;
9239 if (TiedTo != -1) {
9253 Desc.operands()[Inst.getNumOperands()].RegClass != -1) {
9311 if (TiedTo != -1) {
9366 //===----------------------------------------------------------------------===//
9368 //===----------------------------------------------------------------------===//
9593 // This function should be defined after auto-generated include so that we have
9637 // Null is defined as a 32-bit register but
9638 // it should also be enabled with 64-bit operands.
9648 //===----------------------------------------------------------------------===//
9650 //===----------------------------------------------------------------------===//
9662 return Error(S, "expected a 16-bit value");
9671 //===----------------------------------------------------------------------===//
9673 //===----------------------------------------------------------------------===//