Lines Matching defs:RegWidth

1281                     unsigned RegWidth) {
1284       usesSgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);
1287       usesAgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);
1290       usesVgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);
1361   bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,
1364                            unsigned &RegNum, unsigned &RegWidth,
1367                            unsigned &RegNum, unsigned &RegWidth,
1370                            unsigned &RegWidth,
1373                            unsigned &RegWidth,
1376                         unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens);
1379                          unsigned RegWidth, SMLoc Loc);
1386                              unsigned RegWidth);
2499 static int getRegClass(RegisterKind Is, unsigned RegWidth) {
2501     switch (RegWidth) {
2533     switch (RegWidth) {
2547     switch (RegWidth) {
2577     switch (RegWidth) {
2684 bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth,
2691       RegWidth = 64;
2696       RegWidth = 64;
2701       RegWidth = 64;
2706       RegWidth = 64;
2711       RegWidth = 64;
2716       RegWidth = 64;
2725     if (Reg1 != Reg + RegWidth / 32) {
2729     RegWidth += 32;
2809                                         unsigned SubReg, unsigned RegWidth,
2817     AlignSize = std::min(llvm::bit_ceil(RegWidth / 32), 4u);
2826   int RCID = getRegClass(RegKind, RegWidth);
2852 bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth) {
2890   RegWidth = 32 * ((RegHi - RegLo) + 1);
2895                                           unsigned &RegNum, unsigned &RegWidth,
2901     RegWidth = 32;
2910                                           unsigned &RegNum, unsigned &RegWidth,
2943     RegWidth = 32;
2946     if (!ParseRegRange(RegNum, RegWidth))
2950   return getRegularReg(RegKind, RegNum, SubReg, RegWidth, Loc);
2954                                        unsigned &RegWidth,
2967   if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth))
2969   if (RegWidth != 32) {
2992     if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg, Loc))
3002     Reg = getRegularReg(RegKind, RegNum, NoSubRegister, RegWidth, ListLoc);
3008                                           unsigned &RegNum, unsigned &RegWidth,
3014     Reg = ParseSpecialReg(RegKind, RegNum, RegWidth, Tokens);
3016       Reg = ParseRegularReg(RegKind, RegNum, RegWidth, Tokens);
3018     Reg = ParseRegList(RegKind, RegNum, RegWidth, Tokens);
3040                                           unsigned &RegNum, unsigned &RegWidth,
3045   if (ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth, Tokens)) {
3077                                             unsigned RegWidth) {
3087   int64_t NewMax = DwordRegIndex + divideCeil(RegWidth, 32) - 1;
3110   unsigned Reg, RegNum, RegWidth;
3112   if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) {
3116     if (!updateGprCountSymbols(RegKind, RegNum, RegWidth))
3119     KernelScope.usesRegister(RegKind, RegNum, RegWidth);