Lines Matching defs:Operands
1387 void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,
1587 OperandVector &Operands, MCStreamer &Out,
1591 ParseStatus parseOperand(OperandVector &Operands, StringRef Mnemonic,
1595 SMLoc NameLoc, OperandVector &Operands) override;
1598 ParseStatus parseTokenOp(StringRef Name, OperandVector &Operands);
1603 parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
1608 const char *Prefix, OperandVector &Operands,
1613 parseNamedBit(StringRef Name, OperandVector &Operands,
1616 ParseStatus parseCPol(OperandVector &Operands);
1617 ParseStatus parseScope(OperandVector &Operands, int64_t &Scope);
1618 ParseStatus parseTH(OperandVector &Operands, int64_t &TH);
1628 ParseStatus parseImm(OperandVector &Operands, bool HasSP3AbsModifier = false,
1630 ParseStatus parseReg(OperandVector &Operands);
1631 ParseStatus parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod = false,
1633 ParseStatus parseRegOrImmWithFPInputMods(OperandVector &Operands,
1635 ParseStatus parseRegOrImmWithIntInputMods(OperandVector &Operands,
1637 ParseStatus parseRegWithFPInputMods(OperandVector &Operands);
1638 ParseStatus parseRegWithIntInputMods(OperandVector &Operands);
1639 ParseStatus parseVReg32OrOff(OperandVector &Operands);
1640 ParseStatus tryParseIndexKey(OperandVector &Operands,
1642 ParseStatus parseIndexKey8bit(OperandVector &Operands);
1643 ParseStatus parseIndexKey16bit(OperandVector &Operands);
1651 ParseStatus parseFORMAT(OperandVector &Operands);
1654 ParseStatus parseFlatOffset(OperandVector &Operands);
1655 ParseStatus parseR128A16(OperandVector &Operands);
1656 ParseStatus parseBLGP(OperandVector &Operands);
1660 void cvtExp(MCInst &Inst, const OperandVector &Operands);
1663 ParseStatus parseSWaitCnt(OperandVector &Operands);
1667 ParseStatus parseDepCtr(OperandVector &Operands);
1670 ParseStatus parseSDelayALU(OperandVector &Operands);
1672 ParseStatus parseHwreg(OperandVector &Operands);
1720 SMLoc getFlatOffsetLoc(const OperandVector &Operands) const;
1721 SMLoc getSMEMOffsetLoc(const OperandVector &Operands) const;
1722 SMLoc getBLGPLoc(const OperandVector &Operands) const;
1725 const OperandVector &Operands) const;
1726 SMLoc getImmLoc(AMDGPUOperand::ImmTy Type, const OperandVector &Operands) const;
1727 SMLoc getRegLoc(unsigned Reg, const OperandVector &Operands) const;
1728 SMLoc getLitLoc(const OperandVector &Operands,
1730 SMLoc getMandatoryLitLoc(const OperandVector &Operands) const;
1731 SMLoc getConstLoc(const OperandVector &Operands) const;
1732 SMLoc getInstLoc(const OperandVector &Operands) const;
1734 bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
1735 bool validateOffset(const MCInst &Inst, const OperandVector &Operands);
1736 bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
1737 bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);
1739 bool validateConstantBusLimitations(const MCInst &Inst, const OperandVector &Operands);
1741 const OperandVector &Operands);
1745 bool validateMovrels(const MCInst &Inst, const OperandVector &Operands);
1752 bool validateDPP(const MCInst &Inst, const OperandVector &Operands);
1754 bool validateVOPLiteral(const MCInst &Inst, const OperandVector &Operands);
1755 bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands);
1756 bool validateMAISrc2(const MCInst &Inst, const OperandVector &Operands);
1757 bool validateMFMA(const MCInst &Inst, const OperandVector &Operands);
1760 bool validateBLGP(const MCInst &Inst, const OperandVector &Operands);
1761 bool validateDS(const MCInst &Inst, const OperandVector &Operands);
1762 bool validateGWS(const MCInst &Inst, const OperandVector &Operands);
1764 bool validateWaitCnt(const MCInst &Inst, const OperandVector &Operands);
1765 bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
1767 bool validateTHAndScopeBits(const MCInst &Inst, const OperandVector &Operands,
1769 bool validateExeczVcczOperands(const OperandVector &Operands);
1770 bool validateTFE(const MCInst &Inst, const OperandVector &Operands);
1799 bool parseExpr(OperandVector &Operands);
1810 ParseStatus parseCustomOperand(OperandVector &Operands, unsigned MCK);
1812 ParseStatus parseExpTgt(OperandVector &Operands);
1813 ParseStatus parseSendMsg(OperandVector &Operands);
1814 ParseStatus parseInterpSlot(OperandVector &Operands);
1815 ParseStatus parseInterpAttr(OperandVector &Operands);
1816 ParseStatus parseSOPPBrTarget(OperandVector &Operands);
1817 ParseStatus parseBoolReg(OperandVector &Operands);
1828 ParseStatus parseSwizzle(OperandVector &Operands);
1837 ParseStatus parseGPRIdxMode(OperandVector &Operands);
1840 void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false); }
1841 void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true); }
1843 ParseStatus parseOModSI(OperandVector &Operands);
1845 void cvtVOP3(MCInst &Inst, const OperandVector &Operands,
1847 void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);
1848 void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
1849 void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
1850 void cvtSWMMAC(MCInst &Inst, const OperandVector &Operands);
1852 void cvtVOPD(MCInst &Inst, const OperandVector &Operands);
1853 void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,
1855 void cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
1858 void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
1859 void cvtVINTERP(MCInst &Inst, const OperandVector &Operands);
1862 ParseStatus parseDim(OperandVector &Operands);
1864 ParseStatus parseDPP8(OperandVector &Operands);
1865 ParseStatus parseDPPCtrl(OperandVector &Operands);
1866 bool isSupportedDPPCtrl(StringRef Ctrl, const OperandVector &Operands);
1869 void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);
1870 void cvtDPP8(MCInst &Inst, const OperandVector &Operands) {
1871 cvtDPP(Inst, Operands, true);
1873 void cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
1875 void cvtVOP3DPP8(MCInst &Inst, const OperandVector &Operands) {
1876 cvtVOP3DPP(Inst, Operands, true);
1879 ParseStatus parseSDWASel(OperandVector &Operands, StringRef Prefix,
1881 ParseStatus parseSDWADstUnused(OperandVector &Operands);
1882 void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands);
1883 void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands);
1884 void cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands);
1885 void cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands);
1886 void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands);
1887 void cvtSDWA(MCInst &Inst, const OperandVector &Operands,
1892 ParseStatus parseEndpgm(OperandVector &Operands);
1894 ParseStatus parseVOPD(OperandVector &Operands);
3123 ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,
3136 ParseStatus S = parseImm(Operands, HasSP3AbsModifier, HasLit);
3174 Operands.push_back(
3177 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
3204 Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));
3205 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
3210 Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));
3219 ParseStatus AMDGPUAsmParser::parseReg(OperandVector &Operands) {
3225 Operands.push_back(std::move(R));
3231 ParseStatus AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands,
3233 ParseStatus Res = parseReg(Operands);
3238 return parseImm(Operands, HasSP3AbsMod, HasLit);
3330 AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,
3365 Res = parseRegOrImm(Operands, SP3Abs, Lit);
3367 Res = parseReg(Operands);
3372 if (Lit && !Operands.back()->isImm())
3390 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
3399 AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands,
3407 Res = parseRegOrImm(Operands);
3409 Res = parseReg(Operands);
3421 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
3430 ParseStatus AMDGPUAsmParser::parseRegWithFPInputMods(OperandVector &Operands) {
3431 return parseRegOrImmWithFPInputMods(Operands, false);
3434 ParseStatus AMDGPUAsmParser::parseRegWithIntInputMods(OperandVector &Operands) {
3435 return parseRegOrImmWithIntInputMods(Operands, false);
3438 ParseStatus AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) {
3441 Operands.push_back(AMDGPUOperand::CreateImm(this, 0, Loc,
3451 Operands.push_back(std::move(Reg));
3710 const MCInst &Inst, const OperandVector &Operands) {
3791 SMLoc LitLoc = getLitLoc(Operands);
3792 SMLoc RegLoc = getRegLoc(LastSGPR, Operands);
3799 const MCInst &Inst, const OperandVector &Operands) {
3827 assert(ParsedIdx > 0 && ParsedIdx < Operands.size());
3829 auto Loc = ((AMDGPUOperand &)*Operands[ParsedIdx]).getStartLoc();
4053 const OperandVector &Operands) {
4071 ErrLoc = getRegLoc(Reg, Operands);
4073 ErrLoc = getConstLoc(Operands);
4081 const OperandVector &Operands) {
4098 Error(getRegLoc(Reg, Operands),
4107 const OperandVector &Operands) {
4120 Error(getConstLoc(Operands),
4129 const OperandVector &Operands) {
4154 Error(getRegLoc(mc2PseudoReg(Src2Reg), Operands),
4370 SMLoc AMDGPUAsmParser::getFlatOffsetLoc(const OperandVector &Operands) const {
4371 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
4372 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
4380 const OperandVector &Operands) {
4388 return validateFlatOffset(Inst, Operands);
4391 return validateSMEMOffset(Inst, Operands);
4398 Error(getFlatOffsetLoc(Operands),
4405 Error(getFlatOffsetLoc(Operands),
4414 const OperandVector &Operands) {
4425 Error(getFlatOffsetLoc(Operands),
4437 Error(getFlatOffsetLoc(Operands),
4447 SMLoc AMDGPUAsmParser::getSMEMOffsetLoc(const OperandVector &Operands) const {
4449 for (unsigned i = 2, e = Operands.size(); i != e; ++i) {
4450 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
4458 const OperandVector &Operands) {
4481 Error(getSMEMOffsetLoc(Operands),
4602 const OperandVector &Operands) {
4611 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyDppCtrl, Operands);
4627 SMLoc S = getRegLoc(Reg, Operands);
4632 Error(getInstLoc(Operands),
4651 const OperandVector &Operands) {
4682 Error(getLitLoc(Operands), "invalid operand for instruction");
4703 Error(getLitLoc(Operands), "literal operands are not supported");
4708 Error(getLitLoc(Operands, true), "only one unique literal operand is allowed");
4788 SMLoc AMDGPUAsmParser::getBLGPLoc(const OperandVector &Operands) const {
4789 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
4790 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
4798 const OperandVector &Operands) {
4803 SMLoc BLGPLoc = getBLGPLoc(Operands);
4830 const OperandVector &Operands) {
4847 SMLoc RegLoc = getRegLoc(Reg, Operands);
4853 const OperandVector &Operands) {
4858 return validateGWS(Inst, Operands);
4868 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyGDS, Operands);
4878 const OperandVector &Operands) {
4895 SMLoc RegLoc = getRegLoc(Reg, Operands);
4904 const OperandVector &Operands,
4914 return validateTHAndScopeBits(Inst, Operands, CPol);
4919 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
4934 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
4954 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
4968 const OperandVector &Operands,
4977 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
5021 bool AMDGPUAsmParser::validateExeczVcczOperands(const OperandVector &Operands) {
5024 for (auto &Operand : Operands) {
5029 Error(getRegLoc(Reg, Operands),
5038 const OperandVector &Operands) {
5042 SMLoc Loc = getImmLoc(AMDGPUOperand::ImmTyTFE, Operands);
5043 if (Loc != getInstLoc(Operands)) {
5054 const OperandVector &Operands) {
5056 Error(getRegLoc(LDS_DIRECT, Operands), *ErrMsg);
5060 Error(getLitLoc(Operands),
5064 if (!validateVOPLiteral(Inst, Operands)) {
5067 if (!validateConstantBusLimitations(Inst, Operands)) {
5070 if (!validateVOPDRegBankConstraints(Inst, Operands)) {
5074 Error(getImmLoc(AMDGPUOperand::ImmTyClamp, Operands),
5079 Error(getImmLoc(AMDGPUOperand::ImmTyOpSel, Operands),
5084 Error(getImmLoc(AMDGPUOperand::ImmTyNegLo, Operands),
5089 Error(getImmLoc(AMDGPUOperand::ImmTyNegHi, Operands),
5093 if (!validateDPP(Inst, Operands)) {
5098 Error(getImmLoc(AMDGPUOperand::ImmTyD16, Operands),
5103 Error(getImmLoc(AMDGPUOperand::ImmTyDim, Operands),
5113 Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),
5118 Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),
5122 if (!validateMovrels(Inst, Operands)) {
5125 if (!validateOffset(Inst, Operands)) {
5128 if (!validateMAIAccWrite(Inst, Operands)) {
5131 if (!validateMAISrc2(Inst, Operands)) {
5134 if (!validateMFMA(Inst, Operands)) {
5137 if (!validateCoherencyBits(Inst, Operands, IDLoc)) {
5153 if (!validateDS(Inst, Operands)) {
5157 if (!validateBLGP(Inst, Operands)) {
5165 if (!validateWaitCnt(Inst, Operands)) {
5168 if (!validateExeczVcczOperands(Operands)) {
5171 if (!validateTFE(Inst, Operands)) {
5247 static bool isInvalidVOPDY(const OperandVector &Operands,
5249 assert(InvalidOprIdx < Operands.size());
5250 const auto &Op = ((AMDGPUOperand &)*Operands[InvalidOprIdx]);
5252 const auto &PrevOp = ((AMDGPUOperand &)*Operands[InvalidOprIdx - 1]);
5259 OperandVector &Operands,
5267 auto R = MatchInstructionImpl(Operands, Inst, EI, MatchingInlineAsm,
5284 if (!validateInstruction(Inst, IDLoc, Operands)) {
5292 StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();
5308 if (ErrorInfo >= Operands.size()) {
5311 ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();
5315 if (isInvalidVOPDY(Operands, ErrorInfo))
6274 ParseStatus AMDGPUAsmParser::parseOperand(OperandVector &Operands,
6277 ParseStatus Res = parseVOPD(Operands);
6282 Res = MatchOperandParserImpl(Operands, Mnemonic);
6288 // are appending default values to the Operands list. This is only done
6296 unsigned Prefix = Operands.size();
6300 Res = parseReg(Operands);
6315 if (Operands.size() - Prefix > 1) {
6316 Operands.insert(Operands.begin() + Prefix,
6318 Operands.push_back(AMDGPUOperand::CreateToken(this, "]", RBraceLoc));
6324 return parseRegOrImm(Operands);
6363 SMLoc NameLoc, OperandVector &Operands) {
6371 Operands.push_back(AMDGPUOperand::CreateToken(this, Name, NameLoc));
6377 if (IsMIMG && isGFX10Plus() && Operands.size() == 2)
6379 ParseStatus Res = parseOperand(Operands, Name, Mode);
6407 OperandVector &Operands) {
6412 Operands.push_back(AMDGPUOperand::CreateToken(this, Name, S));
6426 const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy,
6439 Operands.push_back(AMDGPUOperand::CreateImm(this, Value, S, ImmTy));
6444 const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy,
6479 Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S, ImmTy));
6484 OperandVector &Operands,
6505 Operands.push_back(AMDGPUOperand::CreateImm(this, Bit, S, ImmTy));
6529 ParseStatus AMDGPUAsmParser::parseCPol(OperandVector &Operands) {
6540 ResTH = parseTH(Operands, TH);
6551 ResScope = parseScope(Operands, Scope);
6566 Operands.push_back(AMDGPUOperand::CreateImm(this, CPolVal, StringLoc,
6571 StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();
6601 Operands.push_back(
6606 ParseStatus AMDGPUAsmParser::parseScope(OperandVector &Operands,
6631 ParseStatus AMDGPUAsmParser::parseTH(OperandVector &Operands, int64_t &TH) {
6693 MCInst& Inst, const OperandVector& Operands,
6700 ((AMDGPUOperand &)*Operands[Idx]).addImmOperands(Inst, 1);
6742 ParseStatus AMDGPUAsmParser::tryParseIndexKey(OperandVector &Operands,
6757 Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, ImmTy));
6761 ParseStatus AMDGPUAsmParser::parseIndexKey8bit(OperandVector &Operands) {
6762 return tryParseIndexKey(Operands, AMDGPUOperand::ImmTyIndexKey8bit);
6765 ParseStatus AMDGPUAsmParser::parseIndexKey16bit(OperandVector &Operands) {
6766 return tryParseIndexKey(Operands, AMDGPUOperand::ImmTyIndexKey16bit);
6933 ParseStatus AMDGPUAsmParser::parseFORMAT(OperandVector &Operands) {
6947 Operands.push_back(
6960 Res = parseRegOrImm(Operands);
6971 auto Size = Operands.size();
6972 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands[Size - 2]);
6984 ParseStatus AMDGPUAsmParser::parseFlatOffset(OperandVector &Operands) {
6986 parseIntWithPrefix("offset", Operands, AMDGPUOperand::ImmTyOffset);
6988 Res = parseIntWithPrefix("inst_offset", Operands,
6994 ParseStatus AMDGPUAsmParser::parseR128A16(OperandVector &Operands) {
6996 parseNamedBit("r128", Operands, AMDGPUOperand::ImmTyR128A16);
6998 Res = parseNamedBit("a16", Operands, AMDGPUOperand::ImmTyA16);
7002 ParseStatus AMDGPUAsmParser::parseBLGP(OperandVector &Operands) {
7004 parseIntWithPrefix("blgp", Operands, AMDGPUOperand::ImmTyBLGP);
7007 parseOperandArrayWithPrefix("neg", Operands, AMDGPUOperand::ImmTyBLGP);
7016 void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {
7023 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
7024 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
7071 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpVM);
7072 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpCompr);
7151 ParseStatus AMDGPUAsmParser::parseSWaitCnt(OperandVector &Operands) {
7166 Operands.push_back(AMDGPUOperand::CreateImm(this, Waitcnt, S));
7232 ParseStatus AMDGPUAsmParser::parseSDelayALU(OperandVector &Operands) {
7246 Operands.push_back(AMDGPUOperand::CreateImm(this, Delay, S));
7319 ParseStatus AMDGPUAsmParser::parseDepCtr(OperandVector &Operands) {
7336 Operands.push_back(AMDGPUOperand::CreateImm(this, DepCtr, Loc));
7386 ParseStatus AMDGPUAsmParser::parseHwreg(OperandVector &Operands) {
7424 Operands.push_back(
7523 ParseStatus AMDGPUAsmParser::parseSendMsg(OperandVector &Operands) {
7546 Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTySendMsg));
7558 ParseStatus AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) {
7574 Operands.push_back(AMDGPUOperand::CreateImm(this, Slot, S,
7579 ParseStatus AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {
7610 Operands.push_back(AMDGPUOperand::CreateImm(this, Attr, S,
7612 Operands.push_back(AMDGPUOperand::CreateImm(
7621 ParseStatus AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) {
7636 Operands.push_back(AMDGPUOperand::CreateImm(this, Id, S,
7735 AMDGPUAsmParser::parseExpr(OperandVector &Operands) {
7744 Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));
7746 Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));
7813 SMLoc AMDGPUAsmParser::getInstLoc(const OperandVector &Operands) const {
7814 return ((AMDGPUOperand &)*Operands[0]).getStartLoc();
7819 const OperandVector &Operands) const {
7820 for (unsigned i = Operands.size() - 1; i > 0; --i) {
7821 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
7825 return getInstLoc(Operands);
7830 const OperandVector &Operands) const {
7832 return getOperandLoc(Test, Operands);
7837 const OperandVector &Operands) const {
7841 return getOperandLoc(Test, Operands);
7844 SMLoc AMDGPUAsmParser::getLitLoc(const OperandVector &Operands,
7849 SMLoc Loc = getOperandLoc(Test, Operands);
7850 if (SearchMandatoryLiterals && Loc == getInstLoc(Operands))
7851 Loc = getMandatoryLitLoc(Operands);
7855 SMLoc AMDGPUAsmParser::getMandatoryLitLoc(const OperandVector &Operands) const {
7859 return getOperandLoc(Test, Operands);
7863 AMDGPUAsmParser::getConstLoc(const OperandVector &Operands) const {
7867 return getOperandLoc(Test, Operands);
8143 ParseStatus AMDGPUAsmParser::parseSwizzle(OperandVector &Operands) {
8158 Operands.push_back(AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTySwizzle));
8218 ParseStatus AMDGPUAsmParser::parseGPRIdxMode(OperandVector &Operands) {
8236 Operands.push_back(
8249 ParseStatus AMDGPUAsmParser::parseSOPPBrTarget(OperandVector &Operands) {
8257 if (!parseExpr(Operands))
8260 AMDGPUOperand &Opr = ((AMDGPUOperand &)*Operands[Operands.size() - 1]);
8279 ParseStatus AMDGPUAsmParser::parseBoolReg(OperandVector &Operands) {
8280 return parseReg(Operands);
8288 const OperandVector &Operands,
8299 for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {
8300 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
8330 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);
8331 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);
8461 ParseStatus AMDGPUAsmParser::parseOModSI(OperandVector &Operands) {
8464 return parseIntWithPrefix("mul", Operands,
8469 return parseIntWithPrefix("div", Operands,
8514 const OperandVector &Operands) {
8515 cvtVOP3P(Inst, Operands);
8519 void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,
8521 cvtVOP3P(Inst, Operands, OptionalIdx);
8538 void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)
8546 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
8549 for (unsigned E = Operands.size(); I != E; ++I) {
8550 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
8564 addOptionalImmOperand(Inst, Operands, OptionalIdx,
8568 addOptionalImmOperand(Inst, Operands, OptionalIdx,
8572 addOptionalImmOperand(Inst, Operands, OptionalIdx,
8576 void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands)
8584 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
8587 for (unsigned E = Operands.size(); I != E; ++I) {
8588 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
8598 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClamp);
8602 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel);
8604 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyWaitEXP);
8636 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
8643 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
8646 for (unsigned E = Operands.size(); I != E; ++I) {
8647 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
8662 addOptionalImmOperand(Inst, Operands, OptionalIdx,
8667 addOptionalImmOperand(Inst, Operands, OptionalIdx,
8671 addOptionalImmOperand(Inst, Operands, OptionalIdx,
8688 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
8690 cvtVOP3(Inst, Operands, OptionalIdx);
8693 void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
8728 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel);
8734 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi,
8740 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegLo);
8744 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi);
8807 void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {
8809 cvtVOP3(Inst, Operands, OptIdx);
8810 cvtVOP3P(Inst, Operands, OptIdx);
8813 static void addSrcModifiersAndSrc(MCInst &Inst, const OperandVector &Operands,
8816 ((AMDGPUOperand &)*Operands[i]).addRegOrImmWithFPInputModsOperands(Inst, 2);
8818 ((AMDGPUOperand &)*Operands[i]).addRegOperands(Inst, 1);
8821 void AMDGPUAsmParser::cvtSWMMAC(MCInst &Inst, const OperandVector &Operands) {
8824 ((AMDGPUOperand &)*Operands[1]).addRegOperands(Inst, 1);
8825 addSrcModifiersAndSrc(Inst, Operands, 2, Opc, AMDGPU::OpName::src0_modifiers);
8826 addSrcModifiersAndSrc(Inst, Operands, 3, Opc, AMDGPU::OpName::src1_modifiers);
8827 ((AMDGPUOperand &)*Operands[1]).addRegOperands(Inst, 1); // srcTiedDef
8828 ((AMDGPUOperand &)*Operands[4]).addRegOperands(Inst, 1); // src2
8831 for (unsigned i = 5; i < Operands.size(); ++i) {
8832 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
8837 addOptionalImmOperand(Inst, Operands, OptIdx,
8841 addOptionalImmOperand(Inst, Operands, OptIdx,
8845 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyClamp);
8847 cvtVOP3P(Inst, Operands, OptIdx);
8854 ParseStatus AMDGPUAsmParser::parseVOPD(OperandVector &Operands) {
8862 Operands.push_back(AMDGPUOperand::CreateToken(this, "::", S));
8866 Operands.push_back(AMDGPUOperand::CreateToken(this, OpYName, OpYLoc));
8875 void AMDGPUAsmParser::cvtVOPD(MCInst &Inst, const OperandVector &Operands) {
8877 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[ParsedOprIdx]);
8989 ParseStatus AMDGPUAsmParser::parseDim(OperandVector &Operands) {
9003 Operands.push_back(AMDGPUOperand::CreateImm(this, Encoding, S,
9012 ParseStatus AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {
9043 Operands.push_back(AMDGPUOperand::CreateImm(this, DPP8, S, AMDGPUOperand::ImmTyDPP8));
9049 const OperandVector &Operands) {
9150 ParseStatus AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
9154 !isSupportedDPPCtrl(getTokenStr(), Operands))
9180 Operands.push_back(
9185 void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
9202 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
9206 for (unsigned E = Operands.size(); I != E; ++I) {
9244 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
9264 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9268 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9272 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
9275 cvtVOP3P(Inst, Operands, OptionalIdx);
9277 cvtVOP3OpSel(Inst, Operands, OptionalIdx);
9279 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel);
9283 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDPP8);
9287 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppCtrl, 0xe4);
9288 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);
9289 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);
9290 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);
9293 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9298 void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {
9304 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
9308 for (unsigned E = Operands.size(); I != E; ++I) {
9316 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
9356 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);
9357 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);
9358 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);
9360 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9370 ParseStatus AMDGPUAsmParser::parseSDWASel(OperandVector &Operands,
9397 Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, Type));
9401 ParseStatus AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {
9422 Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTySDWADstUnused));
9426 void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) {
9427 cvtSDWA(Inst, Operands, SIInstrFlags::VOP1);
9430 void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) {
9431 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2);
9434 void AMDGPUAsmParser::cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands) {
9435 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true, true);
9438 void AMDGPUAsmParser::cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands) {
9439 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, false, true);
9442 void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) {
9443 cvtSDWA(Inst, Operands, SIInstrFlags::VOPC, isVI());
9446 void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
9459 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
9462 for (unsigned E = Operands.size(); I != E; ++I) {
9463 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
9500 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9504 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9508 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9512 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9516 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);
9520 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9524 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0);
9526 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstSel, SdwaSel::DWORD);
9527 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstUnused, DstUnused::UNUSED_PRESERVE);
9528 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);
9529 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD);
9534 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9536 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);
9537 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD);
9568 ParseStatus AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands,
9572 return parseTokenOp("addr64", Operands);
9574 return parseTokenOp("done", Operands);
9576 return parseTokenOp("idxen", Operands);
9578 return parseTokenOp("lds", Operands);
9580 return parseTokenOp("offen", Operands);
9582 return parseTokenOp("off", Operands);
9584 return parseTokenOp("row_en", Operands);
9586 return parseNamedBit("gds", Operands, AMDGPUOperand::ImmTyGDS);
9588 return parseNamedBit("tfe", Operands, AMDGPUOperand::ImmTyTFE);
9590 return tryCustomParseOperand(Operands, MCK);
9652 ParseStatus AMDGPUAsmParser::parseEndpgm(OperandVector &Operands) {
9664 Operands.push_back(