Lines Matching defs:IDLoc
1586 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1734 bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
1746 bool validateMIMGDataSize(const MCInst &Inst, const SMLoc &IDLoc);
1747 bool validateMIMGAddrSize(const MCInst &Inst, const SMLoc &IDLoc);
1766 const SMLoc &IDLoc);
1782 bool checkUnsupportedInstruction(StringRef Name, const SMLoc &IDLoc);
3859 const SMLoc &IDLoc) {
3902 Error(IDLoc, Twine("image data size does not match ") + Modifiers);
3907 const SMLoc &IDLoc) {
3933 Error(IDLoc, "image address size does not match a16");
3971 Error(IDLoc, "image address size does not match dim and a16");
4905 const SMLoc &IDLoc) {
4924 Error(IDLoc, "invalid cache policy for SMEM instruction");
4948 Error(IDLoc, isGFX940() ? "instruction must use sc0"
5053 const SMLoc &IDLoc,
5107 if (!validateMIMGDataSize(Inst, IDLoc)) {
5110 if (!validateMIMGAddrSize(Inst, IDLoc))
5137 if (!validateCoherencyBits(Inst, Operands, IDLoc)) {
5142 Error(IDLoc, getFeatureBits()[AMDGPU::FeatureGFX90AInsts]
5149 Error(IDLoc,
5162 Error(IDLoc, "ABS not allowed in VOP3B instructions");
5203 const SMLoc &IDLoc) {
5218 return Error(IDLoc,
5234 return Error(IDLoc, "instruction requires wavesize=32");
5239 return Error(IDLoc, "instruction not supported on this GPU");
5244 return Error(IDLoc, "invalid instruction" + Suggestion);
5258 bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
5284 if (!validateInstruction(Inst, IDLoc, Operands)) {
5287 Inst.setLoc(IDLoc);
5293 if (checkUnsupportedInstruction(Mnemo, IDLoc)) {
5303 return Error(IDLoc, "operands are not valid for this GPU or mode");
5306 SMLoc ErrorLoc = IDLoc;
5309 return Error(IDLoc, "too few operands for instruction");
5313 ErrorLoc = IDLoc;