Lines Matching defs:DppCtrl

1088     case ImmTyDppCtrl: OS << "DppCtrl"; break;
4606     unsigned DppCtrl = Inst.getOperand(DppCtrlIdx).getImm();
4608     if (!AMDGPU::isLegalDPALU_DPPControl(DppCtrl) &&
8922     return (Imm >= DppCtrl::QUAD_PERM_FIRST && Imm <= DppCtrl::QUAD_PERM_LAST) ||
8923            (Imm >= DppCtrl::ROW_SHL_FIRST && Imm <= DppCtrl::ROW_SHL_LAST) ||
8924            (Imm >= DppCtrl::ROW_SHR_FIRST && Imm <= DppCtrl::ROW_SHR_LAST) ||
8925            (Imm >= DppCtrl::ROW_ROR_FIRST && Imm <= DppCtrl::ROW_ROR_LAST) ||
8926            (Imm == DppCtrl::WAVE_SHL1) ||
8927            (Imm == DppCtrl::WAVE_ROL1) ||
8928            (Imm == DppCtrl::WAVE_SHR1) ||
8929            (Imm == DppCtrl::WAVE_ROR1) ||
8930            (Imm == DppCtrl::ROW_MIRROR) ||
8931            (Imm == DppCtrl::ROW_HALF_MIRROR) ||
8932            (Imm == DppCtrl::BCAST15) ||
8933            (Imm == DppCtrl::BCAST31) ||
8934            (Imm >= DppCtrl::ROW_SHARE_FIRST && Imm <= DppCtrl::ROW_SHARE_LAST) ||
8935            (Imm >= DppCtrl::ROW_XMASK_FIRST && Imm <= DppCtrl::ROW_XMASK_LAST);
9121     .Case("wave_shl",  {DppCtrl::WAVE_SHL1,       1,  1})
9122     .Case("wave_rol",  {DppCtrl::WAVE_ROL1,       1,  1})
9123     .Case("wave_shr",  {DppCtrl::WAVE_SHR1,       1,  1})
9124     .Case("wave_ror",  {DppCtrl::WAVE_ROR1,       1,  1})
9125     .Case("row_shl",   {DppCtrl::ROW_SHL0,        1, 15})
9126     .Case("row_shr",   {DppCtrl::ROW_SHR0,        1, 15})
9127     .Case("row_ror",   {DppCtrl::ROW_ROR0,        1, 15})
9128     .Case("row_share", {DppCtrl::ROW_SHARE_FIRST, 0, 15})
9129     .Case("row_xmask", {DppCtrl::ROW_XMASK_FIRST, 0, 15})
9130     .Case("row_newbcast", {DppCtrl::ROW_NEWBCAST_FIRST, 0, 15})
9136     Val = (Val == 15)? DppCtrl::BCAST15 : DppCtrl::BCAST31;
9164     Val = DppCtrl::ROW_MIRROR;
9166     Val = DppCtrl::ROW_HALF_MIRROR;