Lines Matching defs:CPol
1079 case ImmTyCPol: OS << "CPol"; break;
1768 const unsigned CPol);
4911 unsigned CPol = Inst.getOperand(CPolPos).getImm();
4914 return validateTHAndScopeBits(Inst, Operands, CPol);
4918 if (CPol && (isSI() || isCI())) {
4923 if (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC)) {
4929 if (isGFX90A() && !isGFX940() && (CPol & CPol::SCC)) {
4947 if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) {
4953 if (CPol & CPol::GLC) {
4969 const unsigned CPol) {
4970 const unsigned TH = CPol & AMDGPU::CPol::TH;
4971 const unsigned Scope = CPol & AMDGPU::CPol::SCOPE;
4984 (!(TH & AMDGPU::CPol::TH_ATOMIC_RETURN)))
4991 ((TH == AMDGPU::CPol::TH_NT_RT) || (TH == AMDGPU::CPol::TH_RT_NT) ||
4992 (TH == AMDGPU::CPol::TH_NT_HT)))
4995 if (TH == AMDGPU::CPol::TH_BYPASS) {
4996 if ((Scope != AMDGPU::CPol::SCOPE_SYS &&
4997 CPol & AMDGPU::CPol::TH_REAL_BYPASS) ||
4998 (Scope == AMDGPU::CPol::SCOPE_SYS &&
4999 !(CPol & AMDGPU::CPol::TH_REAL_BYPASS)))
5008 if (!(CPol & AMDGPU::CPol::TH_TYPE_ATOMIC))
5011 if (!(CPol & AMDGPU::CPol::TH_TYPE_STORE))
5014 if (!(CPol & AMDGPU::CPol::TH_TYPE_LOAD))
6515 .Case("nt", AMDGPU::CPol::NT)
6516 .Case("sc0", AMDGPU::CPol::SC0)
6517 .Case("sc1", AMDGPU::CPol::SC1)
6522 .Case("dlc", AMDGPU::CPol::DLC)
6523 .Case("glc", AMDGPU::CPol::GLC)
6524 .Case("scc", AMDGPU::CPol::SCC)
6525 .Case("slc", AMDGPU::CPol::SLC)
6577 unsigned CPol = getCPolKind(getId(), Mnemo, Disabling);
6578 if (!CPol)
6583 if (!isGFX10Plus() && CPol == AMDGPU::CPol::DLC)
6586 if (!isGFX90A() && CPol == AMDGPU::CPol::SCC)
6589 if (Seen & CPol)
6593 Enabled |= CPol;
6595 Seen |= CPol;
6608 Scope = AMDGPU::CPol::SCOPE_CU; // default;
6619 .Case("SCOPE_CU", AMDGPU::CPol::SCOPE_CU)
6620 .Case("SCOPE_SE", AMDGPU::CPol::SCOPE_SE)
6621 .Case("SCOPE_DEV", AMDGPU::CPol::SCOPE_DEV)
6622 .Case("SCOPE_SYS", AMDGPU::CPol::SCOPE_SYS)
6632 TH = AMDGPU::CPol::TH_RT; // default
6641 TH = AMDGPU::CPol::TH_RT;
6646 TH = AMDGPU::CPol::TH_TYPE_ATOMIC;
6648 TH = AMDGPU::CPol::TH_TYPE_LOAD;
6650 TH = AMDGPU::CPol::TH_TYPE_STORE;
6656 TH |= AMDGPU::CPol::TH_REAL_BYPASS;
6659 if (TH & AMDGPU::CPol::TH_TYPE_ATOMIC)
6661 .Case("RETURN", AMDGPU::CPol::TH_ATOMIC_RETURN)
6662 .Case("RT", AMDGPU::CPol::TH_RT)
6663 .Case("RT_RETURN", AMDGPU::CPol::TH_ATOMIC_RETURN)
6664 .Case("NT", AMDGPU::CPol::TH_ATOMIC_NT)
6665 .Case("NT_RETURN", AMDGPU::CPol::TH_ATOMIC_NT |
6666 AMDGPU::CPol::TH_ATOMIC_RETURN)
6667 .Case("CASCADE_RT", AMDGPU::CPol::TH_ATOMIC_CASCADE)
6668 .Case("CASCADE_NT", AMDGPU::CPol::TH_ATOMIC_CASCADE |
6669 AMDGPU::CPol::TH_ATOMIC_NT)
6673 .Case("RT", AMDGPU::CPol::TH_RT)
6674 .Case("NT", AMDGPU::CPol::TH_NT)
6675 .Case("HT", AMDGPU::CPol::TH_HT)
6676 .Case("LU", AMDGPU::CPol::TH_LU)
6677 .Case("RT_WB", AMDGPU::CPol::TH_RT_WB)
6678 .Case("NT_RT", AMDGPU::CPol::TH_NT_RT)
6679 .Case("RT_NT", AMDGPU::CPol::TH_RT_NT)
6680 .Case("NT_HT", AMDGPU::CPol::TH_NT_HT)
6681 .Case("NT_WB", AMDGPU::CPol::TH_NT_WB)
6682 .Case("BYPASS", AMDGPU::CPol::TH_BYPASS)