Lines Matching defs:AMDGPUAsmParser
1 //===- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//
51 class AMDGPUAsmParser;
68 const AMDGPUAsmParser *AsmParser;
71 AMDGPUOperand(KindTy Kind_, const AMDGPUAsmParser *AsmParser_)
1154 static AMDGPUOperand::Ptr CreateImm(const AMDGPUAsmParser *AsmParser,
1169 static AMDGPUOperand::Ptr CreateToken(const AMDGPUAsmParser *AsmParser,
1180 static AMDGPUOperand::Ptr CreateReg(const AMDGPUAsmParser *AsmParser,
1191 static AMDGPUOperand::Ptr CreateExpr(const AMDGPUAsmParser *AsmParser,
1245 // Instruction will error in AMDGPUAsmParser::MatchAndEmitInstruction
1298 class AMDGPUAsmParser : public MCTargetAsmParser {
1398 AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,
1555 return const_cast<AMDGPUAsmParser*>(this)->getContext().getRegisterInfo();
1695 bool Error(AMDGPUAsmParser &Parser, const Twine &Err) const {
1700 virtual bool validate(AMDGPUAsmParser &Parser) const {
2258 const_cast<AMDGPUAsmParser *>(AsmParser)->Warning(Inst.getLoc(),
2489 void AMDGPUAsmParser::createConstantSymbol(StringRef Id, int64_t Val) {
2656 bool AMDGPUAsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
2667 bool AMDGPUAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
2672 ParseStatus AMDGPUAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
2684 bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth,
2768 AMDGPUAsmParser::isRegister(const AsmToken &Token,
2803 AMDGPUAsmParser::isRegister()
2808 unsigned AMDGPUAsmParser::getRegularReg(RegisterKind RegKind, unsigned RegNum,
2852 bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth) {
2894 unsigned AMDGPUAsmParser::ParseSpecialReg(RegisterKind &RegKind,
2909 unsigned AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind,
2953 unsigned AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
3007 bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
3039 bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
3057 AMDGPUAsmParser::getGprCountSymbolName(RegisterKind RegKind) {
3068 void AMDGPUAsmParser::initializeGprCountSymbol(RegisterKind RegKind) {
3075 bool AMDGPUAsmParser::updateGprCountSymbols(RegisterKind RegKind,
3105 AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) {
3123 ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,
3219 ParseStatus AMDGPUAsmParser::parseReg(OperandVector &Operands) {
3231 ParseStatus AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands,
3242 AMDGPUAsmParser::isNamedOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {
3251 AMDGPUAsmParser::isOpcodeModifierWithVal(const AsmToken &Token, const AsmToken &NextToken) const {
3256 AMDGPUAsmParser::isOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {
3261 AMDGPUAsmParser::isRegOrOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {
3279 AMDGPUAsmParser::isModifier() {
3313 AMDGPUAsmParser::parseSP3NegModifier() {
3330 AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,
3399 AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands,
3430 ParseStatus AMDGPUAsmParser::parseRegWithFPInputMods(OperandVector &Operands) {
3434 ParseStatus AMDGPUAsmParser::parseRegWithIntInputMods(OperandVector &Operands) {
3438 ParseStatus AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) {
3458 unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3492 ArrayRef<unsigned> AMDGPUAsmParser::getMatchedVariants() const {
3521 StringRef AMDGPUAsmParser::getMatchedVariantName() const {
3540 unsigned AMDGPUAsmParser::findImplicitSGPRReadInVOP(const MCInst &Inst) const {
3561 bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst,
3621 unsigned AMDGPUAsmParser::getConstantBusLimit(unsigned Opcode) const {
3678 bool AMDGPUAsmParser::usesConstantBus(const MCInst &Inst, unsigned OpIdx) {
3709 bool AMDGPUAsmParser::validateConstantBusLimitations(
3798 bool AMDGPUAsmParser::validateVOPDRegBankConstraints(
3841 bool AMDGPUAsmParser::validateIntClampSupported(const MCInst &Inst) {
3858 bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst,
3906 bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,
3975 bool AMDGPUAsmParser::validateMIMGAtomicDMask(const MCInst &Inst) {
3995 bool AMDGPUAsmParser::validateMIMGGatherDMask(const MCInst &Inst) {
4014 bool AMDGPUAsmParser::validateMIMGMSAA(const MCInst &Inst) {
4052 bool AMDGPUAsmParser::validateMovrels(const MCInst &Inst,
4080 bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst,
4106 bool AMDGPUAsmParser::validateMAISrc2(const MCInst &Inst,
4128 bool AMDGPUAsmParser::validateMFMA(const MCInst &Inst,
4162 bool AMDGPUAsmParser::validateDivScale(const MCInst &Inst) {
4190 bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {
4337 AMDGPUAsmParser::validateLdsDirect(const MCInst &Inst) {
4370 SMLoc AMDGPUAsmParser::getFlatOffsetLoc(const OperandVector &Operands) const {
4379 bool AMDGPUAsmParser::validateOffset(const MCInst &Inst,
4413 bool AMDGPUAsmParser::validateFlatOffset(const MCInst &Inst,
4447 SMLoc AMDGPUAsmParser::getSMEMOffsetLoc(const OperandVector &Operands) const {
4457 bool AMDGPUAsmParser::validateSMEMOffset(const MCInst &Inst,
4489 bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {
4525 bool AMDGPUAsmParser::validateOpSel(const MCInst &Inst) {
4562 bool AMDGPUAsmParser::validateNeg(const MCInst &Inst, int OpName) {
4601 bool AMDGPUAsmParser::validateDPP(const MCInst &Inst,
4643 bool AMDGPUAsmParser::validateVccOperand(unsigned Reg) const {
4650 bool AMDGPUAsmParser::validateVOPLiteral(const MCInst &Inst,
4732 bool AMDGPUAsmParser::validateAGPRLdSt(const MCInst &Inst) const {
4762 bool AMDGPUAsmParser::validateVGPRAlign(const MCInst &Inst) const {
4788 SMLoc AMDGPUAsmParser::getBLGPLoc(const OperandVector &Operands) const {
4797 bool AMDGPUAsmParser::validateBLGP(const MCInst &Inst,
4829 bool AMDGPUAsmParser::validateWaitCnt(const MCInst &Inst,
4852 bool AMDGPUAsmParser::validateDS(const MCInst &Inst,
4877 bool AMDGPUAsmParser::validateGWS(const MCInst &Inst,
4903 bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
4967 bool AMDGPUAsmParser::validateTHAndScopeBits(const MCInst &Inst,
5021 bool AMDGPUAsmParser::validateExeczVcczOperands(const OperandVector &Operands) {
5037 bool AMDGPUAsmParser::validateTFE(const MCInst &Inst,
5052 bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
5186 bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,
5191 bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,
5202 bool AMDGPUAsmParser::checkUnsupportedInstruction(StringRef Mnemo,
5258 bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
5327 bool AMDGPUAsmParser::ParseAsAbsoluteExpression(uint32_t &Ret) {
5339 bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {
5359 bool AMDGPUAsmParser::OutOfRangeError(SMRange Range) {
5363 bool AMDGPUAsmParser::calculateGPRBlocks(
5426 bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
5908 bool AMDGPUAsmParser::ParseDirectiveAMDHSACodeObjectVersion() {
5917 bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,
5960 bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {
5986 bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {
5998 bool AMDGPUAsmParser::ParseDirectiveISAVersion() {
6015 bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() {
6031 bool AMDGPUAsmParser::ParseToEndDirective(const char *AssemblerDirectiveBegin,
6069 bool AMDGPUAsmParser::ParseDirectivePALMetadataBegin() {
6082 bool AMDGPUAsmParser::ParseDirectivePALMetadata() {
6114 bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() {
6164 bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
6210 bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
6274 ParseStatus AMDGPUAsmParser::parseOperand(OperandVector &Operands,
6327 StringRef AMDGPUAsmParser::parseMnemonicSuffix(StringRef Name) {
6361 bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
6406 ParseStatus AMDGPUAsmParser::parseTokenOp(StringRef Name,
6416 ParseStatus AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix,
6425 ParseStatus AMDGPUAsmParser::parseIntWithPrefix(
6443 ParseStatus AMDGPUAsmParser::parseOperandArrayWithPrefix(
6483 ParseStatus AMDGPUAsmParser::parseNamedBit(StringRef Name,
6509 unsigned AMDGPUAsmParser::getCPolKind(StringRef Id, StringRef Mnemo,
6529 ParseStatus AMDGPUAsmParser::parseCPol(OperandVector &Operands) {
6606 ParseStatus AMDGPUAsmParser::parseScope(OperandVector &Operands,
6631 ParseStatus AMDGPUAsmParser::parseTH(OperandVector &Operands, int64_t &TH) {
6694 AMDGPUAsmParser::OptionalImmIndexMap& OptionalIdx,
6706 ParseStatus AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix,
6721 bool AMDGPUAsmParser::tryParseFmt(const char *Pref,
6742 ParseStatus AMDGPUAsmParser::tryParseIndexKey(OperandVector &Operands,
6761 ParseStatus AMDGPUAsmParser::parseIndexKey8bit(OperandVector &Operands) {
6765 ParseStatus AMDGPUAsmParser::parseIndexKey16bit(OperandVector &Operands) {
6771 ParseStatus AMDGPUAsmParser::parseDfmtNfmt(int64_t &Format) {
6803 ParseStatus AMDGPUAsmParser::parseUfmt(int64_t &Format) {
6818 bool AMDGPUAsmParser::matchDfmtNfmt(int64_t &Dfmt,
6841 ParseStatus AMDGPUAsmParser::parseSymbolicSplitFormat(StringRef FormatStr,
6878 ParseStatus AMDGPUAsmParser::parseSymbolicUnifiedFormat(StringRef FormatStr,
6894 ParseStatus AMDGPUAsmParser::parseNumericFormat(int64_t &Format) {
6906 ParseStatus AMDGPUAsmParser::parseSymbolicOrNumericFormat(int64_t &Format) {
6933 ParseStatus AMDGPUAsmParser::parseFORMAT(OperandVector &Operands) {
6984 ParseStatus AMDGPUAsmParser::parseFlatOffset(OperandVector &Operands) {
6994 ParseStatus AMDGPUAsmParser::parseR128A16(OperandVector &Operands) {
7002 ParseStatus AMDGPUAsmParser::parseBLGP(OperandVector &Operands) {
7016 void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {
7103 bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {
7151 ParseStatus AMDGPUAsmParser::parseSWaitCnt(OperandVector &Operands) {
7170 bool AMDGPUAsmParser::parseDelay(int64_t &Delay) {
7232 ParseStatus AMDGPUAsmParser::parseSDelayALU(OperandVector &Operands) {
7261 void AMDGPUAsmParser::depCtrError(SMLoc Loc, int ErrorId,
7281 bool AMDGPUAsmParser::parseDepCtr(int64_t &DepCtr, unsigned &UsedOprMask) {
7319 ParseStatus AMDGPUAsmParser::parseDepCtr(OperandVector &Operands) {
7346 ParseStatus AMDGPUAsmParser::parseHwregFunc(OperandInfoTy &HwReg,
7386 ParseStatus AMDGPUAsmParser::parseHwreg(OperandVector &Operands) {
7398 bool validate(AMDGPUAsmParser &Parser) const override {
7438 AMDGPUAsmParser::parseSendMsgBody(OperandInfoTy &Msg,
7475 AMDGPUAsmParser::validateSendMsg(const OperandInfoTy &Msg,
7523 ParseStatus AMDGPUAsmParser::parseSendMsg(OperandVector &Operands) {
7558 ParseStatus AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) {
7579 ParseStatus AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {
7621 ParseStatus AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) {
7646 AMDGPUAsmParser::isId(const AsmToken &Token, const StringRef Id) const {
7651 AMDGPUAsmParser::isId(const StringRef Id) const {
7656 AMDGPUAsmParser::isToken(const AsmToken::TokenKind Kind) const {
7660 StringRef AMDGPUAsmParser::getId() const {
7665 AMDGPUAsmParser::trySkipId(const StringRef Id) {
7674 AMDGPUAsmParser::trySkipId(const StringRef Pref, const StringRef Id) {
7686 AMDGPUAsmParser::trySkipId(const StringRef Id, const AsmToken::TokenKind Kind) {
7696 AMDGPUAsmParser::trySkipToken(const AsmToken::TokenKind Kind) {
7705 AMDGPUAsmParser::skipToken(const AsmToken::TokenKind Kind,
7715 AMDGPUAsmParser::parseExpr(int64_t &Imm, StringRef Expected) {
7735 AMDGPUAsmParser::parseExpr(OperandVector &Operands) {
7752 AMDGPUAsmParser::parseString(StringRef &Val, const StringRef ErrMsg) {
7763 AMDGPUAsmParser::parseId(StringRef &Val, const StringRef ErrMsg) {
7775 AMDGPUAsmParser::getToken() const {
7779 AsmToken AMDGPUAsmParser::peekToken(bool ShouldSkipSpace) {
7786 AMDGPUAsmParser::peekTokens(MutableArrayRef<AsmToken> Tokens) {
7794 AMDGPUAsmParser::getTokenKind() const {
7799 AMDGPUAsmParser::getLoc() const {
7804 AMDGPUAsmParser::getTokenStr() const {
7809 AMDGPUAsmParser::lex() {
7813 SMLoc AMDGPUAsmParser::getInstLoc(const OperandVector &Operands) const {
7818 AMDGPUAsmParser::getOperandLoc(std::function<bool(const AMDGPUOperand&)> Test,
7829 AMDGPUAsmParser::getImmLoc(AMDGPUOperand::ImmTy Type,
7836 AMDGPUAsmParser::getRegLoc(unsigned Reg,
7844 SMLoc AMDGPUAsmParser::getLitLoc(const OperandVector &Operands,
7855 SMLoc AMDGPUAsmParser::getMandatoryLitLoc(const OperandVector &Operands) const {
7863 AMDGPUAsmParser::getConstLoc(const OperandVector &Operands) const {
7871 AMDGPUAsmParser::parseStructuredOpFields(ArrayRef<StructuredOpField *> Fields) {
7905 bool AMDGPUAsmParser::validateStructuredOpFields(
7930 AMDGPUAsmParser::parseSwizzleOperand(int64_t &Op,
7951 AMDGPUAsmParser::parseSwizzleOperands(const unsigned OpNum, int64_t* Op,
7965 AMDGPUAsmParser::parseSwizzleQuadPerm(int64_t &Imm) {
7981 AMDGPUAsmParser::parseSwizzleBroadcast(int64_t &Imm) {
8009 AMDGPUAsmParser::parseSwizzleReverse(int64_t &Imm) {
8031 AMDGPUAsmParser::parseSwizzleSwap(int64_t &Imm) {
8053 AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) {
8100 AMDGPUAsmParser::parseSwizzleOffset(int64_t &Imm) {
8115 AMDGPUAsmParser::parseSwizzleMacro(int64_t &Imm) {
8143 ParseStatus AMDGPUAsmParser::parseSwizzle(OperandVector &Operands) {
8174 int64_t AMDGPUAsmParser::parseGPRIdxMacro() {
8218 ParseStatus AMDGPUAsmParser::parseGPRIdxMode(OperandVector &Operands) {
8249 ParseStatus AMDGPUAsmParser::parseSOPPBrTarget(OperandVector &Operands) {
8279 ParseStatus AMDGPUAsmParser::parseBoolReg(OperandVector &Operands) {
8287 void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
8382 bool AMDGPUAsmParser::convertDppBoundCtrl(int64_t &BoundCtrl) {
8391 void AMDGPUAsmParser::onBeginOfFile() {
8409 bool AMDGPUAsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
8461 ParseStatus AMDGPUAsmParser::parseOModSI(OperandVector &Operands) {
8513 void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst,
8519 void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,
8538 void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)
8576 void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands)
8636 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
8688 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
8693 void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
8807 void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {
8821 void AMDGPUAsmParser::cvtSWMMAC(MCInst &Inst, const OperandVector &Operands) {
8854 ParseStatus AMDGPUAsmParser::parseVOPD(OperandVector &Operands) {
8875 void AMDGPUAsmParser::cvtVOPD(MCInst &Inst, const OperandVector &Operands) {
8960 bool AMDGPUAsmParser::parseDimId(unsigned &Encoding) {
8989 ParseStatus AMDGPUAsmParser::parseDim(OperandVector &Operands) {
9012 ParseStatus AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {
9048 AMDGPUAsmParser::isSupportedDPPCtrl(StringRef Ctrl,
9073 AMDGPUAsmParser::parseDPPCtrlPerm() {
9103 AMDGPUAsmParser::parseDPPCtrlSel(StringRef Ctrl) {
9150 ParseStatus AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
9185 void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
9298 void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {
9370 ParseStatus AMDGPUAsmParser::parseSDWASel(OperandVector &Operands,
9401 ParseStatus AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {
9426 void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) {
9430 void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) {
9434 void AMDGPUAsmParser::cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands) {
9438 void AMDGPUAsmParser::cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands) {
9442 void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) {
9446 void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
9558 RegisterMCAsmParser<AMDGPUAsmParser> A(getTheR600Target());
9559 RegisterMCAsmParser<AMDGPUAsmParser> B(getTheGCNTarget());
9568 ParseStatus AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands,
9595 unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
9652 ParseStatus AMDGPUAsmParser::parseEndpgm(OperandVector &Operands) {