Lines Matching defs:Src1Regs

2113   SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));
2117     assert(Src0Regs.empty() && Src1Regs.empty());
2123   assert(Src0Regs.size() == Src1Regs.size() &&
2140   if (Src1Regs.empty())
2141     split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg());
2143     setRegsToType(MRI, Src1Regs, HalfTy);
2165   Register Hi = B.buildUMulH(HalfTy, Src0Regs[0], Src1Regs[0]).getReg(0);
2166   Register MulLoHi = B.buildMul(HalfTy, Src0Regs[0], Src1Regs[1]).getReg(0);
2168   Register MulHiLo = B.buildMul(HalfTy, Src0Regs[1], Src1Regs[0]).getReg(0);
2170   B.buildMul(DefRegs[0], Src0Regs[0], Src1Regs[0]);
2334     SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));
2339       assert(Src1Regs.empty() && Src2Regs.empty());
2343     if (Src1Regs.empty())
2344       split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg());
2346       setRegsToType(MRI, Src1Regs, HalfTy);
2356     B.buildSelect(DefRegs[0], CondRegs[0], Src1Regs[0], Src2Regs[0]);
2357     B.buildSelect(DefRegs[1], CondRegs[0], Src1Regs[1], Src2Regs[1]);
2411     SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));
2415       assert(Src0Regs.empty() && Src1Regs.empty());
2420     assert(Src0Regs.size() == Src1Regs.size() &&
2432     if (Src1Regs.empty())
2433       split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg());
2435       setRegsToType(MRI, Src1Regs, HalfTy);
2439     B.buildInstr(Opc, {DefRegs[0]}, {Src0Regs[0], Src1Regs[0]});
2440     B.buildInstr(Opc, {DefRegs[1]}, {Src0Regs[1], Src1Regs[1]});