Lines Matching defs:Src0Regs

2112   SmallVector<Register, 2> Src0Regs(OpdMapper.getVRegs(1));
2117     assert(Src0Regs.empty() && Src1Regs.empty());
2123   assert(Src0Regs.size() == Src1Regs.size() &&
2124          (Src0Regs.empty() || Src0Regs.size() == 2));
2135   if (Src0Regs.empty())
2136     split64BitValueForMapping(B, Src0Regs, HalfTy, MI.getOperand(1).getReg());
2138     setRegsToType(MRI, Src0Regs, HalfTy);
2165   Register Hi = B.buildUMulH(HalfTy, Src0Regs[0], Src1Regs[0]).getReg(0);
2166   Register MulLoHi = B.buildMul(HalfTy, Src0Regs[0], Src1Regs[1]).getReg(0);
2168   Register MulHiLo = B.buildMul(HalfTy, Src0Regs[1], Src1Regs[0]).getReg(0);
2170   B.buildMul(DefRegs[0], Src0Regs[0], Src1Regs[0]);
2410     SmallVector<Register, 2> Src0Regs(OpdMapper.getVRegs(1));
2415       assert(Src0Regs.empty() && Src1Regs.empty());
2420     assert(Src0Regs.size() == Src1Regs.size() &&
2421            (Src0Regs.empty() || Src0Regs.size() == 2));
2427     if (Src0Regs.empty())
2428       split64BitValueForMapping(B, Src0Regs, HalfTy, MI.getOperand(1).getReg());
2430       setRegsToType(MRI, Src0Regs, HalfTy);
2439     B.buildInstr(Opc, {DefRegs[0]}, {Src0Regs[0], Src1Regs[0]});
2440     B.buildInstr(Opc, {DefRegs[1]}, {Src0Regs[1], Src1Regs[1]});