Lines Matching defs:S32
133 const LLT S32 = LLT::scalar(32);
135 assert(MRI.getType(DstReg) == S32);
142 auto True = B.buildConstant(S32, Opc == AMDGPU::G_SEXT ? -1 : 1);
143 auto False = B.buildConstant(S32, 0);
721 LLT S32 = LLT::scalar(32);
729 auto Unmerge = B.buildUnmerge(S32, Src);
737 MRI.setType(DstPart, NumParts == 1 ? Ty : S32);
1096 const LLT S32 = LLT::scalar(32);
1099 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0);
1103 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0);
1249 const LLT S32 = LLT::scalar(32);
1256 VOffsetReg = B.buildConstant(S32, 0).getReg(0);
1257 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0);
1277 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0);
1285 VOffsetReg = B.buildConstant(S32, 0).getReg(0);
1320 VOffsetReg = B.buildCopy(S32, CombinedOffset).getReg(0);
1324 SOffsetReg = B.buildConstant(S32, 0).getReg(0);
1334 const LLT S32 = LLT::scalar(32);
1385 Register VIndex = B.buildConstant(S32, 0).getReg(0);
1459 const LLT S32 = LLT::scalar(32);
1469 if (Ty == S32)
1480 auto UnmergeSOffset = B.buildUnmerge({S32, S32}, ShiftOffset);
1487 auto Zero = B.buildConstant(S32, 0);
1493 Signed ? B.buildSbfx(S32, UnmergeSOffset.getReg(0), Zero, WidthReg)
1494 : B.buildUbfx(S32, UnmergeSOffset.getReg(0), Zero, WidthReg);
1496 Signed ? B.buildAShr(S32, Extract, B.buildConstant(S32, 31)) : Zero;
1501 auto UpperWidth = B.buildConstant(S32, WidthImm - 32);
1504 ? B.buildSbfx(S32, UnmergeSOffset.getReg(1), Zero, UpperWidth)
1505 : B.buildUbfx(S32, UnmergeSOffset.getReg(1), Zero, UpperWidth);
1514 auto ExtShift = B.buildSub(S32, B.buildConstant(S32, 64), WidthReg);
1529 auto OffsetMask = B.buildConstant(S32, maskTrailingOnes<unsigned>(6));
1530 auto ClampOffset = B.buildAnd(S32, OffsetReg, OffsetMask);
1533 auto ShiftWidth = B.buildShl(S32, WidthReg, B.buildConstant(S32, 16));
1538 auto MergedInputs = B.buildOr(S32, ClampOffset, ShiftWidth);
1542 unsigned Opc = Ty == S32 ? (Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32) :
1572 LLT S32 = LLT::scalar(32);
1584 Register DstLo = B.buildMul(S32, Src0, Src1).getReg(0);
1590 DstHi = IsUnsigned ? B.buildUMulH(S32, Src0, Src1).getReg(0)
1591 : B.buildSMulH(S32, Src0, Src1).getReg(0);
1594 Register VSrc0 = B.buildCopy(S32, Src0).getReg(0);
1595 Register VSrc1 = B.buildCopy(S32, Src1).getReg(0);
1600 DstHi = IsUnsigned ? B.buildUMulH(S32, VSrc0, VSrc1).getReg(0)
1601 : B.buildSMulH(S32, VSrc0, VSrc1).getReg(0);
1618 LLT CarryType = DstOnValu ? S1 : S32;
1627 Zero = B.buildConstant(S32, 0).getReg(0);
1631 Carry = B.buildICmp(CmpInst::ICMP_SLT, MulHiInVgpr ? S1 : S32, DstHi, Zero)
1644 DstLo = B.buildCopy(S32, DstLo).getReg(0);
1645 DstHi = B.buildCopy(S32, DstHi).getReg(0);
1650 auto Unmerge = B.buildUnmerge(S32, Src2);
1664 auto AddLo = B.buildUAddo(S32, CarryType, DstLo, Src2Lo);
1670 auto AddHi = B.buildUAdde(S32, CarryType, DstHi, Src2Hi, CarryLo);
1722 const LLT S32 = LLT::scalar(32);
1723 auto Bitcast = B.buildBitcast(S32, Src);
1726 auto ExtLo = B.buildSExtInReg(S32, Bitcast, 16);
1727 auto ShiftHi = B.buildAShr(S32, Bitcast, B.buildConstant(S32, 16));
1731 auto ShiftHi = B.buildLShr(S32, Bitcast, B.buildConstant(S32, 16));
1733 auto ExtLo = B.buildAnd(S32, Bitcast, B.buildConstant(S32, 0xffff));
1774 const LLT S32 = LLT::scalar(32);
1777 return B.buildMergeLikeInstr(LLT::fixed_vector(NumElts, S32), WideRegs)
1801 const LLT S32 = LLT::scalar(32);
1827 BaseReg = B.buildConstant(S32, Overflow).getReg(0);
1829 auto OverflowVal = B.buildConstant(S32, Overflow);
1830 BaseReg = B.buildAdd(S32, BaseReg, OverflowVal).getReg(0);
1836 BaseReg = B.buildConstant(S32, 0).getReg(0);
1881 const LLT S32 = LLT::scalar(32);
1885 auto MaterializedOffset = B.buildConstant(S32, ConstOffset);
1887 auto Add = B.buildAdd(S32, WaterfallIdx, MaterializedOffset);
1942 LLT S32 = LLT::scalar(32);
1954 LLT CCTy = (CCBank == AMDGPU::SGPRRegBank) ? S32 : LLT::scalar(1);
1957 Idx = B.buildCopy(S32, Idx)->getOperand(0).getReg();
1975 auto IC = B.buildConstant(S32, I);
2040 LLT S32 = LLT::scalar(32);
2055 LLT CCTy = (CCBank == AMDGPU::SGPRRegBank) ? S32 : LLT::scalar(1);
2058 Idx = B.buildCopy(S32, Idx)->getOperand(0).getReg();
2076 auto IC = B.buildConstant(S32, I);
2220 const LLT S32 = LLT::scalar(32);
2255 if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized)
2284 const LLT S32 = LLT::scalar(32);
2285 Register NewDstReg = MRI.createGenericVirtualRegister(S32);
2290 Register NewSrcReg = MRI.createGenericVirtualRegister(S32);
2320 const LLT S32 = LLT::scalar(32);
2321 Register NewCondReg = MRI.createGenericVirtualRegister(S32);
2370 const LLT S32 = LLT::scalar(32);
2371 Register NewCondReg = MRI.createGenericVirtualRegister(S32);
2494 const LLT S32 = LLT::scalar(32);
2504 auto Lo = B.buildInstr(AMDGPU::G_ABS, {S32}, {WideSrcLo});
2505 auto Hi = B.buildInstr(AMDGPU::G_ABS, {S32}, {WideSrcHi});
2520 auto Lo = B.buildInstr(MI.getOpcode(), {S32}, {WideSrc0Lo, WideSrc1Lo});
2521 auto Hi = B.buildInstr(MI.getOpcode(), {S32}, {WideSrc0Hi, WideSrc1Hi});
2527 if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized)
2534 if (Helper.widenScalar(MI, 1, S32) != LegalizerHelper::Legalized)
2558 const LLT S32 = LLT::scalar(32);
2585 MRI.setType(Op0L, S32);
2591 MRI.setType(Op1L, S32);
2612 const LLT S32 = LLT::scalar(32);
2628 auto Freeze = B.buildFreeze(S32, SrcRegs[0]);
2633 B.buildAShr(DstRegs[1], DstRegs[0], B.buildConstant(S32, 31));
2654 const LLT S32 = LLT::scalar(32);
2656 if (Ty == S32)
2664 if (Helper.narrowScalar(MI, 1, S32) != LegalizerHelper::Legalized)
2678 const LLT S32 = LLT::scalar(32);
2680 if (Ty == S32)
2697 auto X = B.buildInstr(NewOpc, {S32}, {SrcRegs[Idx]});
2698 auto Y = B.buildInstr(NewOpc, {S32}, {SrcRegs[Idx ^ 1]});
2703 Y = B.buildInstr(AddOpc, {S32}, {Y, B.buildConstant(S32, 32)});
2798 const LLT S32 = LLT::scalar(32);
2864 auto One = B.buildConstant(S32, 1);
2875 auto IdxLo = B.buildShl(S32, BaseIdxReg, One);
2876 auto IdxHi = B.buildAdd(S32, IdxLo, One);
2902 Register TmpReg0 = MRI.createGenericVirtualRegister(S32);
2903 Register TmpReg1 = MRI.createGenericVirtualRegister(S32);
2975 const LLT S32 = LLT::scalar(32);
2979 auto One = B.buildConstant(S32, 1);
2988 auto IdxLo = B.buildShl(S32, BaseIdxReg, One);
2989 auto IdxHi = B.buildAdd(S32, IdxLo, One);