Lines Matching defs:OpdMapper
1056 const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper,
1065 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
1138 SmallVector<Register, 16> DefRegs(OpdMapper.getVRegs(0));
1139 SmallVector<Register, 1> SrcRegs(OpdMapper.getVRegs(1));
1171 const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper,
1218 const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper,
1227 applyDefaultMapping(OpdMapper);
1330 MachineIRBuilder &B, const OperandsMapper &OpdMapper) const {
1331 MachineInstr &MI = OpdMapper.getMI();
1332 MachineRegisterInfo &MRI = OpdMapper.getMRI();
1339 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
1341 OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank;
1448 const OperandsMapper &OpdMapper,
1450 MachineInstr &MI = OpdMapper.getMI();
1451 MachineRegisterInfo &MRI = OpdMapper.getMRI();
1454 applyDefaultMapping(OpdMapper);
1467 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
1554 MachineIRBuilder &B, const OperandsMapper &OpdMapper) const {
1555 MachineInstr &MI = OpdMapper.getMI();
1556 MachineRegisterInfo &MRI = OpdMapper.getMRI();
1559 applyDefaultMapping(OpdMapper);
1744 const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper, unsigned OpIdx) {
1745 SmallVector<unsigned, 1> SrcReg(OpdMapper.getVRegs(OpIdx));
1748 OpdMapper.getMI().getOperand(OpIdx).setReg(SrcReg[0]);
1923 const OperandsMapper &OpdMapper) const {
1930 *OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank;
1945 *OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
1947 *OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
1962 SmallVector<Register, 2> DstRegs(OpdMapper.getVRegs(0));
2021 const OperandsMapper &OpdMapper) const {
2028 *OpdMapper.getInstrMapping().getOperandMapping(3).BreakDown[0].RegBank;
2043 *OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2045 *OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
2047 *OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank;
2063 SmallVector<Register, 2> InsRegs(OpdMapper.getVRegs(2));
2110 MachineIRBuilder &B, const OperandsMapper &OpdMapper) const {
2111 SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
2112 SmallVector<Register, 2> Src0Regs(OpdMapper.getVRegs(1));
2113 SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));
2118 applyDefaultMapping(OpdMapper);
2126 MachineRegisterInfo &MRI = OpdMapper.getMRI();
2127 MachineInstr &MI = OpdMapper.getMI();
2177 MachineIRBuilder &B, const OperandsMapper &OpdMapper) const {
2178 MachineInstr &MI = OpdMapper.getMI();
2181 MachineRegisterInfo &MRI = OpdMapper.getMRI();
2191 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2194 SmallVector<Register, 1> DefRegs(OpdMapper.getVRegs(0));
2222 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2224 applyDefaultMapping(OpdMapper);
2248 substituteSimpleCopyRegs(OpdMapper, 0);
2276 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2301 SmallVector<Register, 1> DefRegs(OpdMapper.getVRegs(0));
2311 SmallVector<Register, 1> CondRegs(OpdMapper.getVRegs(1));
2333 SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
2334 SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));
2335 SmallVector<Register, 2> Src2Regs(OpdMapper.getVRegs(3));
2367 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2391 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2409 SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
2410 SmallVector<Register, 2> Src0Regs(OpdMapper.getVRegs(1));
2411 SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));
2480 applyMappingSMULU64(B, OpdMapper);
2490 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2553 applyDefaultMapping(OpdMapper);
2563 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2608 SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1));
2618 SmallVector<Register, 2> DstRegs(OpdMapper.getVRegs(0));
2649 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2673 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2690 SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1));
2716 assert(OpdMapper.getVRegs(1).empty());
2719 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
2730 SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
2755 SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
2791 SmallVector<Register, 2> DstRegs(OpdMapper.getVRegs(0));
2793 assert(OpdMapper.getVRegs(1).empty() && OpdMapper.getVRegs(2).empty());
2802 if (foldExtractEltToCmpSelect(B, MI, OpdMapper))
2806 = OpdMapper.getInstrMapping().getOperandMapping(0);
2809 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
2811 OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank;
2837 applyDefaultMapping(OpdMapper);
2922 SmallVector<Register, 2> InsRegs(OpdMapper.getVRegs(2));
2927 assert(OpdMapper.getVRegs(0).empty());
2928 assert(OpdMapper.getVRegs(3).empty());
2930 if (substituteSimpleCopyRegs(OpdMapper, 1))
2933 if (foldInsertEltToCmpSelect(B, MI, OpdMapper))
2937 OpdMapper.getInstrMapping().getOperandMapping(3).BreakDown[0].RegBank;
2995 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2997 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
2999 OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank;
3060 applyDefaultMapping(OpdMapper);
3076 applyDefaultMapping(OpdMapper);
3083 applyDefaultMapping(OpdMapper);
3088 applyDefaultMapping(OpdMapper);
3097 applyMappingSBufferLoad(B, OpdMapper);
3104 substituteSimpleCopyRegs(OpdMapper, 2);
3106 assert(OpdMapper.getVRegs(0).empty());
3107 assert(OpdMapper.getVRegs(3).empty());
3115 assert(OpdMapper.getVRegs(0).empty());
3116 assert(OpdMapper.getVRegs(2).empty());
3117 assert(OpdMapper.getVRegs(3).empty());
3119 substituteSimpleCopyRegs(OpdMapper, 4); // VGPR input val
3130 applyDefaultMapping(OpdMapper);
3143 applyDefaultMapping(OpdMapper);
3148 substituteSimpleCopyRegs(OpdMapper, 2);
3149 substituteSimpleCopyRegs(OpdMapper, 3);
3155 applyMappingBFE(B, OpdMapper, true);
3158 applyMappingBFE(B, OpdMapper, false);
3164 applyDefaultMapping(OpdMapper);
3184 applyMappingImage(B, MI, OpdMapper, RSrcIntrin->RsrcArg);
3189 applyDefaultMapping(OpdMapper);
3200 assert(OpdMapper.getVRegs(0).empty());
3201 substituteSimpleCopyRegs(OpdMapper, 3);
3209 substituteSimpleCopyRegs(OpdMapper, 1);
3240 applyDefaultMapping(OpdMapper);
3248 applyDefaultMapping(OpdMapper);
3255 applyDefaultMapping(OpdMapper);
3260 applyDefaultMapping(OpdMapper);
3266 applyDefaultMapping(OpdMapper);
3270 assert(OpdMapper.getVRegs(1).empty());
3296 applyMappingImage(B, MI, OpdMapper, RSrcIntrin->RsrcArg);
3404 if (applyMappingLoad(B, OpdMapper, MI))
3409 applyMappingDynStackAlloc(B, OpdMapper, MI);
3412 applyDefaultMapping(OpdMapper);
3417 applyMappingBFE(B, OpdMapper, /*Signed*/ true);
3420 applyMappingBFE(B, OpdMapper, /*Signed*/ false);
3424 applyMappingMAD_64_32(B, OpdMapper);
3443 applyDefaultMapping(OpdMapper);
3450 return applyDefaultMapping(OpdMapper);