Lines Matching defs:S64
287 static const LLT S64 = LLT::scalar(64);
335 static std::initializer_list<LLT> AllScalarTypes = {S32, S64, S96, S128,
689 S32, S64
693 S32, S64, S16
697 S32, S64, S16, V2S16
708 .legalFor({S32, S64, V2S16, S16, V4S16, S1, S128, S256})
725 .legalFor({S64, S32, S16, V2S16})
743 .legalFor({S64, S32, S16, V2S16})
840 .customFor({S32, S64})
841 .clampScalar(0, S32, S64)
862 .legalFor({S32, S1, S64, V2S32, S16, V2S16, V4S16})
863 .clampScalar(0, S32, S64)
881 .legalFor({S1, S32, S64, S16, GlobalPtr,
884 .clampScalar(0, S32, S64)
888 .legalFor({S32, S64, S16})
889 .clampScalar(0, S16, S64);
913 getActionDefinitionsBuilder({G_GET_FPENV, G_SET_FPENV}).customFor({S64});
923 .legalFor({S32, S64});
925 .customFor({S32, S64});
927 .customFor({S32, S64});
951 .clampScalar(0, S16, S64)
955 .clampScalar(0, S16, S64)
959 .clampScalar(0, S32, S64)
968 .clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64);
972 .clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64);
976 .clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64);
982 .clampScalar(0, S16, S64);
987 .customFor({S32, S64})
991 .legalFor({S32, S64, S16})
993 .clampScalar(0, S16, S64);
996 .legalFor({{S32, S32}, {S64, S32}, {S16, S16}})
1003 .customFor({{S32, S32}, {S64, S32}, {S16, S16}, {S16, S32}})
1008 .customFor({S32, S64, S16})
1015 .customFor({S64})
1016 .legalFor({S32, S64})
1018 .clampScalar(0, S32, S64);
1021 .legalFor({S32, S64})
1023 .clampScalar(0, S32, S64);
1027 .legalFor({{S32, S32}, {S64, S32}})
1029 .clampScalar(0, S32, S64)
1034 .customFor({{S32, S32}, {S64, S32}})
1042 .legalFor({{S32, S64}, {S16, S32}})
1047 .legalFor({{S64, S32}, {S32, S16}})
1048 .narrowScalarFor({{S64, S16}}, changeTo(0, S32))
1057 .lowerFor({S64, V2S16});
1063 .lowerFor({S64, S16, V2S16});
1068 .clampScalar(0, S32, S64);
1083 FRem.customFor({S16, S32, S64});
1086 .customFor({S32, S64});
1102 .legalFor({{S64, S32}, {S32, S16}, {S64, S16},
1103 {S32, S1}, {S64, S1}, {S16, S1}})
1105 .clampScalar(0, S32, S64)
1110 .legalFor({{S32, S32}, {S64, S32}, {S16, S32}})
1112 .customFor({{S32, S64}, {S64, S64}});
1115 IToFP.clampScalar(1, S32, S64)
1121 .legalFor({{S32, S32}, {S32, S64}, {S32, S16}})
1122 .customFor({{S64, S32}, {S64, S64}})
1123 .narrowScalarFor({{S64, S16}}, changeTo(0, S32));
1147 .legalFor({S16, S32, S64})
1148 .clampScalar(0, S16, S64)
1153 .legalFor({S32, S64})
1154 .clampScalar(0, S32, S64)
1160 .customFor({S64})
1161 .clampScalar(0, S32, S64)
1172 .legalIf(all(sameSize(0, 1), typeInSet(1, {S64, S32})))
1189 {S1}, {S32, S64, GlobalPtr, LocalPtr, ConstantPtr, PrivatePtr, FlatPtr})
1191 {S32}, {S32, S64, GlobalPtr, LocalPtr, ConstantPtr, PrivatePtr, FlatPtr});
1198 .clampScalar(1, S32, S64)
1211 .clampScalar(1, S32, S64)
1244 .legalFor({{S32, S32}, {S32, S64}})
1247 .clampScalar(1, S32, S64)
1272 .clampScalar(1, S32, S64)
1279 .legalFor({{S32, S32}, {S32, S64}})
1282 .clampScalar(1, S32, S64)
1288 .legalFor({{S32, S32}, {S32, S64}})
1290 .clampScalar(1, S32, S64)
1295 // S64 is only legal on SALU, and needs to be broken into 32-bit elements in
1298 .legalFor({S32, S64})
1299 .clampScalar(0, S32, S64)
1351 .legalForCartesianProduct(AddrSpaces64, {S64})
1367 .legalForCartesianProduct(AddrSpaces64, {S64})
1434 {S64, GlobalPtr, S64, GlobalAlign32},
1441 {S64, LocalPtr, S64, 32},
1455 {S64, ConstantPtr, S64, GlobalAlign32},
1634 {S64, GlobalPtr}, {S64, LocalPtr},
1635 {S32, RegionPtr}, {S64, RegionPtr}});
1637 Atomics.legalFor({{S32, FlatPtr}, {S64, FlatPtr}});
1645 Atomic.legalFor({{S64, LocalPtr}});
1660 {S64, GlobalPtr},
1661 {S64, FlatPtr}
1692 .customFor({{S32, GlobalPtr}, {S64, GlobalPtr},
1693 {S32, FlatPtr}, {S64, FlatPtr}})
1694 .legalFor({{S32, LocalPtr}, {S64, LocalPtr},
1695 {S32, RegionPtr}, {S64, RegionPtr}});
1700 .legalForCartesianProduct({S32, S64, S16, V2S32, V2S16, V4S16, GlobalPtr,
1705 .clampScalar(0, S16, S64)
1719 .legalFor({{S32, S32}, {S64, S32}});
1740 Shifts.clampScalar(0, S16, S64);
1752 Shifts.clampScalar(0, S32, S64);
1807 .clampScalar(EltTypeIdx, S32, S64)
1808 .clampScalar(VecTypeIdx, S32, S64)
1866 .legalForCartesianProduct(AllS64Vectors, {S64})
1981 // S64 is only legal on SALU, and needs to be broken into 32-bit elements in
1984 .legalFor({{S32}, {S64}});
1993 SextInReg.lowerFor({{S32}, {S64}, {S16}});
1997 SextInReg.lowerFor({{S32}, {S64}});
2002 .clampScalar(0, S32, S64)
2030 .legalFor({S64});
2032 getActionDefinitionsBuilder(G_READSTEADYCOUNTER).legalFor({S64});
2043 .legalFor({{S32, S32}, {S64, S32}})
2045 .clampScalar(0, S32, S64)
2198 const LLT S64 = LLT::scalar(64);
2216 Register Dst = MRI.createGenericVirtualRegister(S64);
2452 const LLT S64 = LLT::scalar(64);
2455 assert(MRI.getType(Src) == S64);
2461 auto Trunc = B.buildIntrinsicTrunc(S64, Src);
2463 const auto Zero = B.buildFConstant(S64, 0.0);
2464 const auto One = B.buildFConstant(S64, 1.0);
2468 auto Add = B.buildSelect(S64, And, One, Zero);
2515 const LLT S64 = LLT::scalar(64);
2518 assert(MRI.getType(Src) == S64);
2534 const auto FractMask = B.buildConstant(S64, (UINT64_C(1) << FractBits) - 1);
2539 auto SignBit64 = B.buildMergeLikeInstr(S64, {Zero32, SignBit});
2541 auto Shr = B.buildAShr(S64, FractMask, Exp);
2542 auto Not = B.buildNot(S64, Shr);
2543 auto Tmp0 = B.buildAnd(S64, Src, Not);
2549 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0);
2562 const LLT S64 = LLT::scalar(64);
2565 assert(MRI.getType(Src) == S64);
2570 if (MRI.getType(Dst) == S64) {
2571 auto CvtHi = Signed ? B.buildSITOFP(S64, Unmerge.getReg(1))
2572 : B.buildUITOFP(S64, Unmerge.getReg(1));
2574 auto CvtLo = B.buildUITOFP(S64, Unmerge.getReg(0));
2575 auto LdExp = B.buildFLdexp(S64, CvtHi, ThirtyTwo);
2599 auto Norm = B.buildShl(S64, Src, ShAmt);
2620 const LLT S64 = LLT::scalar(64);
2624 assert((SrcLT == S32 || SrcLT == S64) && MRI.getType(Dst) == S64);
2649 if (SrcLT == S64) {
2651 S64, llvm::bit_cast<double>(UINT64_C(/*2^-32*/ 0x3df0000000000000)));
2653 S64, llvm::bit_cast<double>(UINT64_C(/*-2^32*/ 0xc1f0000000000000)));
2665 auto Hi = (Signed && SrcLT == S64) ? B.buildFPTOSI(S32, FloorMul)
2671 Sign = B.buildMergeLikeInstr(S64, {Sign, Sign});
2673 B.buildSub(Dst, B.buildXor(S64, B.buildMergeLikeInstr(S64, {Lo, Hi}), Sign),
3882 const LLT S64 = LLT::scalar(64);
3894 Zero64 = B.buildConstant(S64, 0).getReg(0);
3996 Tmp = B.buildAnyExt(S64, LocalAccum[0]).getReg(0);
3999 Tmp = B.buildMergeLikeInstr(S64, LocalAccum).getReg(0);
4002 Tmp = B.buildZExt(S64, LocalAccum[0]).getReg(0);
4017 auto Mad = B.buildInstr(AMDGPU::G_AMDGPU_MAD_U64_U32, {S64, S1},
4456 LLT S64 = LLT::scalar(64);
4462 if (DstTy == S64)
4562 const LLT S64 = LLT::scalar(64);
4568 auto Rcp = B.buildMergeLikeInstr(S64, {RcpLo, RcpHi});
4570 auto Zero64 = B.buildConstant(S64, 0);
4571 auto NegDenom = B.buildSub(S64, Zero64, Denom);
4573 auto MulLo1 = B.buildMul(S64, NegDenom, Rcp);
4574 auto MulHi1 = B.buildUMulH(S64, Rcp, MulLo1);
4582 auto Add1 = B.buildMergeLikeInstr(S64, {Add1_Lo, Add1_Hi});
4584 auto MulLo2 = B.buildMul(S64, NegDenom, Add1);
4585 auto MulHi2 = B.buildUMulH(S64, Add1, MulLo2);
4593 auto Add2 = B.buildMergeLikeInstr(S64, {Add2_Lo, Add2_Hi});
4599 auto MulHi3 = B.buildUMulH(S64, Numer, Add2);
4600 auto Mul3 = B.buildMul(S64, Denom, MulHi3);
4607 auto Sub1 = B.buildMergeLikeInstr(S64, {Sub1_Lo, Sub1_Hi});
4630 auto Sub2 = B.buildMergeLikeInstr(S64, {Sub2_Lo, Sub2_Hi});
4632 auto One64 = B.buildConstant(S64, 1);
4633 auto Add3 = B.buildAdd(S64, MulHi3, One64);
4643 auto Add4 = B.buildAdd(S64, Add3, One64);
4648 auto Sub3 = B.buildMergeLikeInstr(S64, {Sub3_Lo, Sub3_Hi});
4655 S64, B.buildICmp(CmpInst::ICMP_NE, S1, C6, Zero32), Add4, Add3);
4662 S64, B.buildICmp(CmpInst::ICMP_NE, S1, C6, Zero32), Sub3, Sub2);
4690 const LLT S64 = LLT::scalar(64);
4699 else if (Ty == S64)
4711 const LLT S64 = LLT::scalar(64);
4715 if (Ty != S32 && Ty != S64)
5036 LLT S64 = LLT::scalar(64);
5039 auto One = B.buildFConstant(S64, 1.0);
5041 auto DivScale0 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1})
5047 auto NegDivScale0 = B.buildFNeg(S64, DivScale0.getReg(0), Flags);
5049 auto Rcp = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S64})
5053 auto Fma0 = B.buildFMA(S64, NegDivScale0, Rcp, One, Flags);
5054 auto Fma1 = B.buildFMA(S64, Rcp, Fma0, Rcp, Flags);
5055 auto Fma2 = B.buildFMA(S64, NegDivScale0, Fma1, One, Flags);
5057 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1})
5063 auto Fma3 = B.buildFMA(S64, Fma1, Fma2, Fma1, Flags);
5064 auto Mul = B.buildFMul(S64, DivScale1.getReg(0), Fma3, Flags);
5065 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags);
5088 auto Fmas = B.buildIntrinsic(Intrinsic::amdgcn_div_fmas, {S64})
6831 const LLT S64 = LLT::scalar(64);
6863 Register Temp = B.buildLoad(S64, LoadAddr, *MMO).getReg(0);
7137 if (MRI.getType(Src) != S64)
7157 if (MRI.getType(Src) != S64)