Lines Matching full:const
51 const GCNSubtarget *Subtarget;
54 AMDGPUInstructionSelector(const GCNSubtarget &STI,
55 const AMDGPURegisterBankInfo &RBI,
56 const AMDGPUTargetMachine &TM);
59 static const char *getName();
72 bool isSGPR(Register Reg) const;
74 bool isInstrUniform(const MachineInstr &MI) const;
75 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
77 const RegisterBank *getArtifactRegBank(
78 Register Reg, const MachineRegisterInfo &MRI,
79 const TargetRegisterInfo &TRI) const;
82 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
85 const TargetRegisterClass &SubRC,
86 unsigned SubIdx) const;
88 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
89 bool selectCOPY(MachineInstr &I) const;
90 bool selectPHI(MachineInstr &I) const;
91 bool selectG_TRUNC(MachineInstr &I) const;
92 bool selectG_SZA_EXT(MachineInstr &I) const;
93 bool selectG_FPEXT(MachineInstr &I) const;
94 bool selectG_CONSTANT(MachineInstr &I) const;
95 bool selectG_FNEG(MachineInstr &I) const;
96 bool selectG_FABS(MachineInstr &I) const;
97 bool selectG_AND_OR_XOR(MachineInstr &I) const;
98 bool selectG_ADD_SUB(MachineInstr &I) const;
99 bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
100 bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
101 bool selectG_EXTRACT(MachineInstr &I) const;
102 bool selectG_FMA_FMAD(MachineInstr &I) const;
103 bool selectG_MERGE_VALUES(MachineInstr &I) const;
104 bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
105 bool selectG_BUILD_VECTOR(MachineInstr &I) const;
106 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
107 bool selectG_INSERT(MachineInstr &I) const;
108 bool selectG_SBFX_UBFX(MachineInstr &I) const;
110 bool selectInterpP1F16(MachineInstr &MI) const;
111 bool selectWritelane(MachineInstr &MI) const;
112 bool selectDivScale(MachineInstr &MI) const;
113 bool selectIntrinsicCmp(MachineInstr &MI) const;
114 bool selectBallot(MachineInstr &I) const;
115 bool selectRelocConstant(MachineInstr &I) const;
116 bool selectGroupStaticSize(MachineInstr &I) const;
117 bool selectReturnAddress(MachineInstr &I) const;
118 bool selectG_INTRINSIC(MachineInstr &I) const;
120 bool selectEndCfIntrinsic(MachineInstr &MI) const;
121 bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
122 bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
123 bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
124 bool selectSBarrier(MachineInstr &MI) const;
125 bool selectDSBvhStackIntrinsic(MachineInstr &MI) const;
128 const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
129 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
130 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
131 bool selectG_ICMP_or_FCMP(MachineInstr &I) const;
132 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
133 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
134 SmallVectorImpl<GEPInfo> &AddrInfo) const;
136 void initM0(MachineInstr &I) const;
137 bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
138 bool selectG_SELECT(MachineInstr &I) const;
139 bool selectG_BRCOND(MachineInstr &I) const;
140 bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
141 bool selectG_PTRMASK(MachineInstr &I) const;
142 bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
143 bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
144 bool selectBufferLoadLds(MachineInstr &MI) const;
145 bool selectGlobalLoadLds(MachineInstr &MI) const;
146 bool selectBVHIntrinsic(MachineInstr &I) const;
147 bool selectSMFMACIntrin(MachineInstr &I) const;
148 bool selectWaveAddress(MachineInstr &I) const;
149 bool selectStackRestore(MachineInstr &MI) const;
150 bool selectNamedBarrierInst(MachineInstr &I, Intrinsic::ID IID) const;
151 bool selectSBarrierSignalIsfirst(MachineInstr &I, Intrinsic::ID IID) const;
152 bool selectSBarrierLeave(MachineInstr &I) const;
157 bool OpSel = false) const;
161 bool ForceVGPR = false) const;
164 selectVCSRC(MachineOperand &Root) const;
167 selectVSRC0(MachineOperand &Root) const;
170 selectVOP3Mods0(MachineOperand &Root) const;
172 selectVOP3BMods0(MachineOperand &Root) const;
174 selectVOP3OMods(MachineOperand &Root) const;
176 selectVOP3Mods(MachineOperand &Root) const;
178 selectVOP3ModsNonCanonicalizing(MachineOperand &Root) const;
180 selectVOP3BMods(MachineOperand &Root) const;
182 ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
185 selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI,
186 bool IsDOT = false) const;
189 selectVOP3PMods(MachineOperand &Root) const;
192 selectVOP3PModsDOT(MachineOperand &Root) const;
195 selectVOP3PModsNeg(MachineOperand &Root) const;
198 selectWMMAOpSelVOP3PMods(MachineOperand &Root) const;
201 selectWMMAModsF32NegAbs(MachineOperand &Root) const;
203 selectWMMAModsF16Neg(MachineOperand &Root) const;
205 selectWMMAModsF16NegAbs(MachineOperand &Root) const;
207 selectWMMAVISrc(MachineOperand &Root) const;
209 selectSWMMACIndex8(MachineOperand &Root) const;
211 selectSWMMACIndex16(MachineOperand &Root) const;
214 selectVOP3OpSelMods(MachineOperand &Root) const;
217 selectVINTERPMods(MachineOperand &Root) const;
219 selectVINTERPModsHi(MachineOperand &Root) const;
222 int64_t *Offset) const;
224 selectSmrdImm(MachineOperand &Root) const;
226 selectSmrdImm32(MachineOperand &Root) const;
228 selectSmrdSgpr(MachineOperand &Root) const;
230 selectSmrdSgprImm(MachineOperand &Root) const;
233 uint64_t FlatVariant) const;
236 selectFlatOffset(MachineOperand &Root) const;
238 selectGlobalOffset(MachineOperand &Root) const;
240 selectScratchOffset(MachineOperand &Root) const;
243 selectGlobalSAddr(MachineOperand &Root) const;
246 selectScratchSAddr(MachineOperand &Root) const;
248 uint64_t ImmOffset) const;
250 selectScratchSVAddr(MachineOperand &Root) const;
253 selectMUBUFScratchOffen(MachineOperand &Root) const;
255 selectMUBUFScratchOffset(MachineOperand &Root) const;
257 bool isDSOffsetLegal(Register Base, int64_t Offset) const;
259 unsigned Size) const;
260 bool isFlatScratchBaseLegal(Register Addr) const;
261 bool isFlatScratchBaseLegalSV(Register Addr) const;
262 bool isFlatScratchBaseLegalSVImm(Register Addr) const;
265 selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
267 selectDS1Addr1Offset(MachineOperand &Root) const;
270 selectDS64Bit4ByteAligned(MachineOperand &Root) const;
273 selectDS128Bit8ByteAligned(MachineOperand &Root) const;
276 unsigned size) const;
278 selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
282 const MachineRegisterInfo &MRI) const;
292 bool shouldUseAddr64(MUBUFAddressData AddrData) const;
295 Register &SOffset, int64_t &ImmOffset) const;
297 MUBUFAddressData parseMUBUFAddress(Register Src) const;
301 int64_t &Offset) const;
304 Register &SOffset, int64_t &Offset) const;
307 selectBUFSOffset(MachineOperand &Root) const;
310 selectMUBUFAddr64(MachineOperand &Root) const;
313 selectMUBUFOffset(MachineOperand &Root) const;
315 ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
316 ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
317 ComplexRendererFns selectSMRDBufferSgprImm(MachineOperand &Root) const;
320 bool &Matched) const;
321 ComplexRendererFns selectVOP3PMadMixModsExt(MachineOperand &Root) const;
322 ComplexRendererFns selectVOP3PMadMixMods(MachineOperand &Root) const;
324 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
325 int OpIdx = -1) const;
327 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
328 int OpIdx) const;
330 void renderOpSelTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
331 int OpIdx) const;
333 void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
334 int OpIdx) const;
336 void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
337 int OpIdx) const;
339 void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
340 int OpIdx) const;
341 void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
342 int OpIdx) const;
343 void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
344 int OpIdx) const;
345 void renderExtractCpolSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
346 int OpIdx) const;
348 void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
349 int OpIdx) const;
351 void renderFPPow2ToExponent(MachineInstrBuilder &MIB, const MachineInstr &MI,
352 int OpIdx) const;
354 bool isInlineImmediate(const APInt &Imm) const;
355 bool isInlineImmediate(const APFloat &Imm) const;
359 bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;
361 const SIInstrInfo &TII;
362 const SIRegisterInfo &TRI;
363 const AMDGPURegisterBankInfo &RBI;
364 const AMDGPUTargetMachine &TM;
365 const GCNSubtarget &STI;