Lines Matching full:mib
557 MachineInstrBuilder MIB =
561 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef()));
562 MIB.addImm(SubRegs[I]);
702 auto MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_AND_B32_e32), TmpReg)
705 if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI))
708 MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_LSHL_OR_B32_e64), Dst)
712 if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI))
753 auto MIB = BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst)
759 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
861 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), DstReg)
866 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
931 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::V_WRITELANE_B32), VDst);
938 MIB.addReg(Val);
939 MIB.addImm(ConstSelect->Value.getSExtValue() &
949 MIB.addImm(ConstVal->Value.getSExtValue());
950 MIB.addReg(LaneSelect);
952 MIB.addReg(Val);
959 BuildMI(*MBB, *MIB, DL, TII.get(AMDGPU::COPY), AMDGPU::M0)
961 MIB.addReg(AMDGPU::M0);
965 MIB.addReg(VDstIn);
968 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
997 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), Dst0)
1009 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
1485 auto MIB = BuildMI(*MBB, &I, DL, TII.get(Mov), DstReg);
1489 MIB.addImm(MFI->getLDSSize());
1494 MIB.addGlobalAddress(GV, 0, SIInstrInfo::MO_ABS32_LO);
1498 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
1709 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(gwsIntrinToOpcode(IID)));
1713 MIB.addReg(VSrc);
1719 MIB.addImm(ImmOffset)
1722 TII.enforceOperandRCAlignment(*MIB, AMDGPU::OpName::data0);
1752 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), MI.getOperand(0).getReg())
1757 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
1970 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opcode))
1981 MIB.addDef(TmpReg);
1988 MIB.addDef(VDataOut); // vdata output
1993 MIB.addReg(VDataIn); // vdata input
1999 MIB.addReg(SrcOp.getReg());
2003 MIB.addReg(MI.getOperand(ArgOffset + Intr->RsrcIndex).getReg());
2005 MIB.addReg(MI.getOperand(ArgOffset + Intr->SampIndex).getReg());
2007 MIB.addImm(DMask); // dmask
2010 MIB.addImm(DimInfo->Encoding);
2012 MIB.addImm(Unorm);
2014 MIB.addImm(CPol);
2015 MIB.addImm(IsA16 && // a16 or r128
2018 MIB.addImm(IsA16 ? -1 : 0);
2021 MIB.addImm(TFE); // tfe
2028 MIB.addImm(LWE); // lwe
2030 MIB.addImm(DimInfo->DA ? -1 : 0);
2032 MIB.addImm(IsD16 ? -1 : 0);
2035 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
2036 TII.enforceOperandRCAlignment(*MIB, AMDGPU::OpName::vaddr);
2055 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::DS_BVH_STACK_RTN_B32), Dst0)
2064 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
2923 auto MIB = BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_AND_B64), DstReg)
2928 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
3232 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc));
3236 BuildMI(*MBB, &*MIB, DL, TII.get(AMDGPU::REG_SEQUENCE), IdxReg)
3242 MIB.addReg(IdxReg);
3244 MIB.addReg(VIndex);
3246 MIB.addReg(VOffset);
3249 MIB.add(MI.getOperand(1)); // rsrc
3250 MIB.add(MI.getOperand(5 + OpOffset)); // soffset
3251 MIB.add(MI.getOperand(6 + OpOffset)); // imm offset
3253 MIB.addImm(Aux & AMDGPU::CPol::ALL); // cpol
3254 MIB.addImm(Aux & AMDGPU::CPol::SWZ_pregfx12 ? 1 : 0); // swz
3272 MIB.setMemRefs({LoadMMO, StoreMMO});
3275 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
3351 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc))
3355 MIB.addReg(VOffset);
3357 MIB.add(MI.getOperand(4)) // offset
3374 MIB.setMemRefs({LoadMMO, StoreMMO});
3377 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
3652 [=](MachineInstrBuilder &MIB) { MIB.add(Root); }
3716 [=](MachineInstrBuilder &MIB) { MIB.add(Root); }
3727 [=](MachineInstrBuilder &MIB) {
3728 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB));
3730 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods
3731 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
3732 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
3745 [=](MachineInstrBuilder &MIB) {
3746 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB));
3748 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods
3749 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
3750 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
3757 [=](MachineInstrBuilder &MIB) { MIB.add(Root); },
3758 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
3759 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
3770 [=](MachineInstrBuilder &MIB) {
3771 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB));
3773 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
3785 [=](MachineInstrBuilder &MIB) {
3786 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB));
3788 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
3800 [=](MachineInstrBuilder &MIB) {
3801 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB));
3803 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
3814 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); },
3854 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
3855 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
3869 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
3870 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
3885 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
3899 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
3922 auto MIB = B.buildInstr(AMDGPU::REG_SEQUENCE)
3925 MIB.addReg(Elts[i]);
3926 MIB.addImm(SIRegisterInfo::getSubRegFromChannel(i));
3928 return MIB->getOperand(0).getReg();
3988 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
3989 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}};
4014 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
4015 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}};
4047 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
4048 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}};
4056 return {{[=](MachineInstrBuilder &MIB) {
4057 MIB.addImm(FPValReg->Value.bitcastToAPInt().getSExtValue());
4069 {[=](MachineInstrBuilder &MIB) { MIB.addImm(ICst.getSExtValue()); }}};
4092 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
4093 [=](MachineInstrBuilder &MIB) { MIB.addImm(Key); } // index_key
4114 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
4115 [=](MachineInstrBuilder &MIB) { MIB.addImm(Key); } // index_key
4127 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
4128 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
4142 [=](MachineInstrBuilder &MIB) {
4143 MIB.addReg(
4144 copyToVGPRIfSrcFolded(Src, Mods, Root, MIB, /* ForceVGPR */ true));
4146 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods
4160 [=](MachineInstrBuilder &MIB) {
4161 MIB.addReg(
4162 copyToVGPRIfSrcFolded(Src, Mods, Root, MIB, /* ForceVGPR */ true));
4164 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods
4256 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); },
4257 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }}};
4276 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
4277 [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); }
4287 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); },
4288 [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}};
4298 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Base); },
4299 [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); },
4300 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }}};
4334 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); },
4335 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); },
4344 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); },
4345 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); },
4354 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrWithOffset.first); },
4355 [=](MachineInstrBuilder &MIB) { MIB.addImm(PtrWithOffset.second); },
4400 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrBase); }, // saddr
4401 [=](MachineInstrBuilder &MIB) {
4402 MIB.addReg(HighBits);
4404 [=](MachineInstrBuilder &MIB) { MIB.addImm(SplitImmOffset); },
4436 return {{[=](MachineInstrBuilder &MIB) { // saddr
4437 MIB.addReg(SAddr);
4439 [=](MachineInstrBuilder &MIB) { // voffset
4440 MIB.addReg(VOffset);
4442 [=](MachineInstrBuilder &MIB) { // offset
4443 MIB.addImm(ImmOffset);
4465 [=](MachineInstrBuilder &MIB) { MIB.addReg(AddrDef->Reg); }, // saddr
4466 [=](MachineInstrBuilder &MIB) { MIB.addReg(VOffset); }, // voffset
4467 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset
4493 [=](MachineInstrBuilder &MIB) { MIB.addFrameIndex(FI); }, // saddr
4494 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset
4525 [=](MachineInstrBuilder &MIB) { MIB.addReg(SAddr); }, // saddr
4526 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset
4591 [=](MachineInstrBuilder &MIB) { MIB.addReg(RHS); }, // vaddr
4592 [=](MachineInstrBuilder &MIB) { MIB.addFrameIndex(FI); }, // saddr
4593 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset
4601 [=](MachineInstrBuilder &MIB) { MIB.addReg(RHS); }, // vaddr
4602 [=](MachineInstrBuilder &MIB) { MIB.addReg(LHS); }, // saddr
4603 [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset
4626 return {{[=](MachineInstrBuilder &MIB) { // rsrc
4627 MIB.addReg(Info->getScratchRSrcReg());
4629 [=](MachineInstrBuilder &MIB) { // vaddr
4630 MIB.addReg(HighBits);
4632 [=](MachineInstrBuilder &MIB) { // soffset
4635 MIB.addImm(0);
4637 [=](MachineInstrBuilder &MIB) { // offset
4638 MIB.addImm(Offset & MaxOffset);
4668 return {{[=](MachineInstrBuilder &MIB) { // rsrc
4669 MIB.addReg(Info->getScratchRSrcReg());
4671 [=](MachineInstrBuilder &MIB) { // vaddr
4673 MIB.addFrameIndex(*FI);
4675 MIB.addReg(VAddr);
4677 [=](MachineInstrBuilder &MIB) { // soffset
4680 MIB.addImm(0);
4682 [=](MachineInstrBuilder &MIB) { // offset
4683 MIB.addImm(Offset);
4834 [=](MachineInstrBuilder &MIB) { // rsrc
4835 MIB.addReg(Info->getScratchRSrcReg());
4837 [=](MachineInstrBuilder &MIB) { // soffset
4838 MIB.addReg(WaveBase);
4840 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // offset
4859 [=](MachineInstrBuilder &MIB) { // rsrc
4860 MIB.addReg(Info->getScratchRSrcReg());
4862 [=](MachineInstrBuilder &MIB) { // soffset
4863 MIB.addReg(WaveBase);
4865 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } // offset
4874 [=](MachineInstrBuilder &MIB) { // rsrc
4875 MIB.addReg(Info->getScratchRSrcReg());
4877 [=](MachineInstrBuilder &MIB) { // soffset
4878 MIB.addImm(0);
4880 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); } // offset
4920 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); },
4921 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }
4942 [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); },
4943 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); },
4944 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset+1); }
4999 static void addZeroImm(MachineInstrBuilder &MIB) {
5000 MIB.addImm(0);
5213 [=](MachineInstrBuilder &MIB) { // rsrc
5214 MIB.addReg(RSrcReg);
5216 [=](MachineInstrBuilder &MIB) { // vaddr
5217 MIB.addReg(VAddr);
5219 [=](MachineInstrBuilder &MIB) { // soffset
5221 MIB.addReg(SOffset);
5223 MIB.addReg(AMDGPU::SGPR_NULL);
5225 MIB.addImm(0);
5227 [=](MachineInstrBuilder &MIB) { // offset
5228 MIB.addImm(Offset);
5246 [=](MachineInstrBuilder &MIB) { // rsrc
5247 MIB.addReg(RSrcReg);
5249 [=](MachineInstrBuilder &MIB) { // soffset
5251 MIB.addReg(SOffset);
5253 MIB.addReg(AMDGPU::SGPR_NULL);
5255 MIB.addImm(0);
5257 [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }, // offset
5272 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}};
5296 return {{ [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } }};
5312 return {{ [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); } }};
5332 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); },
5333 [=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedOffset); }}};
5465 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
5466 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
5478 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
5479 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
5586 MachineInstrBuilder MIB;
5588 MIB = BuildMI(*MBB, &I, DL, TII.get(Opc));
5591 MIB.addDef(I.getOperand(0).getReg());
5594 MIB.addImm(*BarValImm);
5613 void AMDGPUInstructionSelector::renderTruncImm32(MachineInstrBuilder &MIB,
5618 MIB.addImm(MI.getOperand(1).getCImm()->getSExtValue());
5621 void AMDGPUInstructionSelector::renderNegateImm(MachineInstrBuilder &MIB,
5626 MIB.addImm(-MI.getOperand(1).getCImm()->getSExtValue());
5629 void AMDGPUInstructionSelector::renderBitcastImm(MachineInstrBuilder &MIB,
5636 MIB.addImm(Op.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue());
5639 MIB.addImm(Op.getCImm()->getSExtValue());
5643 void AMDGPUInstructionSelector::renderPopcntImm(MachineInstrBuilder &MIB,
5648 MIB.addImm(MI.getOperand(1).getCImm()->getValue().popcount());
5653 void AMDGPUInstructionSelector::renderTruncTImm(MachineInstrBuilder &MIB,
5656 MIB.addImm(MI.getOperand(OpIdx).getImm());
5659 void AMDGPUInstructionSelector::renderOpSelTImm(MachineInstrBuilder &MIB,
5663 MIB.addImm(MI.getOperand(OpIdx).getImm() ? (int64_t)SISrcMods::OP_SEL_0 : 0);
5666 void AMDGPUInstructionSelector::renderExtractCPol(MachineInstrBuilder &MIB,
5670 MIB.addImm(MI.getOperand(OpIdx).getImm() &
5675 void AMDGPUInstructionSelector::renderExtractSWZ(MachineInstrBuilder &MIB,
5682 MIB.addImm(Swizzle);
5686 MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const {
5691 MIB.addImm(Cpol | AMDGPU::CPol::GLC);
5694 void AMDGPUInstructionSelector::renderFrameIndex(MachineInstrBuilder &MIB,
5697 MIB.addFrameIndex(MI.getOperand(1).getIndex());
5700 void AMDGPUInstructionSelector::renderFPPow2ToExponent(MachineInstrBuilder &MIB,
5706 MIB.addImm(ExpVal);