Lines Matching defs:SrcRC

114   const TargetRegisterClass *SrcRC
116   if (!DstRC || DstRC != SrcRC)
120          RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI);
147       const TargetRegisterClass *SrcRC
158         Register MaskedReg = MRI->createVirtualRegister(SrcRC);
164         bool IsSGPR = TRI.isSGPRClass(SrcRC);
179         MRI->setRegClass(SrcReg, SrcRC);
518   const TargetRegisterClass *SrcRC =
520   if (!SrcRC)
524   SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubReg);
525   if (!SrcRC)
529                                     *SrcRC, I.getOperand(1));
564     const TargetRegisterClass *SrcRC
566     if (SrcRC && !RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI))
593   const TargetRegisterClass *SrcRC =
595   if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
601   ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8);
608     SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]);
609     if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
2217   const TargetRegisterClass *SrcRC =
2221   if (!SrcRC || !DstRC)
2224   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||
2303       = TRI.getSubClassWithSubReg(SrcRC, SubRegIdx);
2307     if (SrcWithSubRC != SrcRC) {
2364     const TargetRegisterClass *SrcRC =
2370     Register UndefReg = MRI->createVirtualRegister(SrcRC);
2380            RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI);
2408     const TargetRegisterClass &SrcRC = InReg && DstSize > 32 ?
2410     if (!RBI.constrainGenericRegister(SrcReg, SrcRC, *MRI))
2936   const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(Ty, *SrcRB);
2941       !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||
3053   const TargetRegisterClass *SrcRC =
3057   if (!SrcRC || !DstRC)
3059   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||
3070       *MRI, TRI, SrcRC, IdxReg, DstTy.getSizeInBits() / 8, *KB);
3101       TII.getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*SrcRC), true);