Lines Matching defs:PtrBase

1730   Register PtrBase = MI.getOperand(2).getReg();
1731   LLT PtrTy = MRI->getType(PtrBase);
1735   std::tie(PtrBase, Offset) = selectDS1Addr1OffsetImpl(MI.getOperand(2));
1738   if (!isDSOffsetLegal(PtrBase, Offset)) {
1739     PtrBase = MI.getOperand(2).getReg();
1748     .addReg(PtrBase);
1749   if (!RBI.constrainGenericRegister(PtrBase, AMDGPU::SReg_32RegClass, *MRI))
4313   Register PtrBase;
4315   std::tie(PtrBase, ConstOffset) =
4326   return std::pair(PtrBase, ConstOffset);
4363   Register PtrBase;
4369   std::tie(PtrBase, ConstOffset) = getPtrBaseWithConstantOffset(Addr, *MRI);
4374       Addr = PtrBase;
4377       auto PtrBaseDef = getDefSrcRegIgnoringCopies(PtrBase, *MRI);
4400                 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrBase); }, // saddr
4474   Register PtrBase;
4480   std::tie(PtrBase, ConstOffset) = getPtrBaseWithConstantOffset(Addr, *MRI);
4485     Addr = PtrBase;
4551   Register PtrBase;
4557   std::tie(PtrBase, ConstOffset) = getPtrBaseWithConstantOffset(Addr, *MRI);
4562     Addr = PtrBase;
4649     Register PtrBase;
4651     std::tie(PtrBase, ConstOffset) = getPtrBaseWithConstantOffset(VAddr, *MRI);
4655            KB->signBitIsZero(PtrBase))) {
4656         const MachineInstr *PtrBaseDef = MRI->getVRegDef(PtrBase);
4660           VAddr = PtrBase;
4892   Register PtrBase;
4894   std::tie(PtrBase, Offset) =
4898     if (isDSOffsetLegal(PtrBase, Offset)) {
4900       return std::pair(PtrBase, Offset);
4957   Register PtrBase;
4959   std::tie(PtrBase, Offset) =
4965     if (isDSOffset2Legal(PtrBase, OffsetValue0, OffsetValue1, Size)) {
4967       return std::pair(PtrBase, OffsetValue0 / Size);
5071   Register PtrBase;
5074   std::tie(PtrBase, Offset) = getPtrBaseWithConstantOffset(Src, *MRI);
5076     Data.N0 = PtrBase;