Lines Matching defs:Mods
3662 unsigned Mods = 0;
3667 Mods |= SISrcMods::NEG;
3675 Mods |= SISrcMods::NEG;
3682 Mods |= SISrcMods::ABS;
3686 Mods |= SISrcMods::OP_SEL_0;
3688 return std::pair(Src, Mods);
3692 Register Src, unsigned Mods, MachineOperand Root, MachineInstr *InsertPt,
3694 if ((Mods != 0 || ForceVGPR) &&
3723 unsigned Mods;
3724 std::tie(Src, Mods) = selectVOP3ModsImpl(Root);
3728 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB));
3730 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods
3739 unsigned Mods;
3740 std::tie(Src, Mods) = selectVOP3ModsImpl(Root,
3746 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB));
3748 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods
3766 unsigned Mods;
3767 std::tie(Src, Mods) = selectVOP3ModsImpl(Root);
3771 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB));
3773 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
3781 unsigned Mods;
3782 std::tie(Src, Mods) = selectVOP3ModsImpl(Root, /*IsCanonicalizing=*/false);
3786 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB));
3788 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
3795 unsigned Mods;
3796 std::tie(Src, Mods) = selectVOP3ModsImpl(Root, /*IsCanonicalizing=*/true,
3801 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB));
3803 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
3821 unsigned Mods = 0;
3828 Mods ^= (SISrcMods::NEG | SISrcMods::NEG_HI);
3839 Mods |= SISrcMods::OP_SEL_1;
3841 return std::pair(Src, Mods);
3850 unsigned Mods;
3851 std::tie(Src, Mods) = selectVOP3PModsImpl(Root.getReg(), MRI);
3855 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
3865 unsigned Mods;
3866 std::tie(Src, Mods) = selectVOP3PModsImpl(Root.getReg(), MRI, true);
3870 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
3881 unsigned Mods = SISrcMods::OP_SEL_1;
3883 Mods ^= SISrcMods::NEG;
3885 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
3894 unsigned Mods = SISrcMods::OP_SEL_1;
3896 Mods |= SISrcMods::OP_SEL_0;
3899 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
3931 static void selectWMMAModsNegAbs(unsigned ModOpcode, unsigned &Mods,
3936 Mods |= SISrcMods::NEG;
3950 Mods |= SISrcMods::NEG_HI;
3956 Mods |= SISrcMods::NEG_HI;
3964 unsigned Mods = SISrcMods::OP_SEL_1;
3983 selectWMMAModsNegAbs(ModOpcode, Mods, EltsF32, Src, Root.getParent(),
3989 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}};
3995 unsigned Mods = SISrcMods::OP_SEL_1;
4008 Mods |= SISrcMods::NEG;
4009 Mods |= SISrcMods::NEG_HI;
4015 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}};
4021 unsigned Mods = SISrcMods::OP_SEL_1;
4042 selectWMMAModsNegAbs(ModOpcode, Mods, EltsV2F16, Src, Root.getParent(),
4048 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}};
4122 unsigned Mods;
4123 std::tie(Src, Mods) = selectVOP3ModsImpl(Root);
4128 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
4135 unsigned Mods;
4136 std::tie(Src, Mods) = selectVOP3ModsImpl(Root,
4144 copyToVGPRIfSrcFolded(Src, Mods, Root, MIB, /* ForceVGPR */ true));
4146 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods
4153 unsigned Mods;
4154 std::tie(Src, Mods) = selectVOP3ModsImpl(Root,
4162 copyToVGPRIfSrcFolded(Src, Mods, Root, MIB, /* ForceVGPR */ true));
4164 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods
5395 unsigned Mods;
5396 std::tie(Src, Mods) = selectVOP3ModsImpl(Root);
5417 if ((Mods & SISrcMods::ABS) == 0) {
5423 Mods ^= SISrcMods::NEG;
5426 Mods |= SISrcMods::ABS;
5437 Mods |= SISrcMods::OP_SEL_1;
5440 Mods |= SISrcMods::OP_SEL_0;
5451 return {Src, Mods};
5458 unsigned Mods;
5460 std::tie(Src, Mods) = selectVOP3PMadMixModsImpl(Root, Matched);
5466 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
5473 unsigned Mods;
5475 std::tie(Src, Mods) = selectVOP3PMadMixModsImpl(Root, Matched);
5479 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods