Lines Matching defs:IdxReg

3012                         const TargetRegisterClass *SuperRC, Register IdxReg,
3018       AMDGPU::getBaseWithConstantOffset(MRI, IdxReg, &KnownBits);
3023     IdxBaseReg = IdxReg;
3031     return std::pair(IdxReg, SubRegs[0]);
3039   Register IdxReg = MI.getOperand(2).getReg();
3046   const RegisterBank *IdxRB = RBI.getRegBank(IdxReg, *MRI, TRI);
3061       !RBI.constrainGenericRegister(IdxReg, AMDGPU::SReg_32RegClass, *MRI))
3069   std::tie(IdxReg, SubReg) = computeIndirectRegIndex(
3070       *MRI, TRI, SrcRC, IdxReg, DstTy.getSizeInBits() / 8, *KB);
3077       .addReg(IdxReg);
3092       .addReg(IdxReg);
3104       .addReg(IdxReg)
3117   Register IdxReg = MI.getOperand(3).getReg();
3126   const RegisterBank *IdxRB = RBI.getRegBank(IdxReg, *MRI, TRI);
3143       !RBI.constrainGenericRegister(IdxReg, AMDGPU::SReg_32RegClass, *MRI))
3150   std::tie(IdxReg, SubReg) =
3151       computeIndirectRegIndex(*MRI, TRI, VecRC, IdxReg, ValSize / 8, *KB);
3161       .addReg(IdxReg);
3178       .addReg(IdxReg)
3235     Register IdxReg = MRI->createVirtualRegister(TRI.getVGPR64Class());
3236     BuildMI(*MBB, &*MIB, DL, TII.get(AMDGPU::REG_SEQUENCE), IdxReg)
3242     MIB.addReg(IdxReg);