Lines Matching defs:HiReg
1425 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
1426 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B32), HiReg).addImm(0);
1430 .addReg(HiReg)
2235 Register HiReg = MRI->createVirtualRegister(DstRC);
2238 BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), HiReg)
2247 .addReg(HiReg) // $src0
2261 .addReg(HiReg);
2264 .addReg(HiReg)
2425 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
2428 BuildMI(MBB, I, DL, TII.get(AMDGPU::S_ASHR_I32), HiReg)
2433 BuildMI(MBB, I, DL, TII.get(AMDGPU::S_MOV_B32), HiReg)
2439 .addReg(HiReg)
2584 Register HiReg = MRI->createVirtualRegister(RC);
2589 BuildMI(*BB, &I, DL, TII.get(Opcode), HiReg)
2595 .addReg(HiReg)
2639 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
2645 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), HiReg)
2653 .addReg(HiReg)
2677 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
2687 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), HiReg)
2695 .addReg(HiReg)
2959 Register HiReg = MRI->createVirtualRegister(&RegRC);
2965 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), HiReg)
2987 MaskedHi = HiReg;
2995 .addReg(HiReg)