Lines Matching defs:CCReg

1308   Register CCReg = I.getOperand(0).getReg();
1309   if (!isVCC(CCReg, *MRI)) {
1316     BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CCReg)
1320         RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32RegClass, *MRI);
2132   Register CCReg = CCOp.getReg();
2133   if (!isVCC(CCReg, *MRI)) {
2137             .addReg(CCReg);
2142     if (!MRI->getRegClassOrNull(CCReg))
2143         MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI));
5487   Register CCReg = I.getOperand(0).getReg();
5502   BuildMI(*MBB, &I, DL, TII.get(AMDGPU::COPY), CCReg).addReg(AMDGPU::SCC);
5505   return RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32_XM0_XEXECRegClass,
5603   Register CCReg = I.getOperand(0).getReg();
5606   BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CCReg).addReg(AMDGPU::SCC);
5609   return RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32_XM0_XEXECRegClass,