Lines Matching defs:AddrDef

3326     auto AddrDef = getDefSrcRegIgnoringCopies(Addr, *MRI);
3327     if (isSGPR(AddrDef->Reg)) {
3328       Addr = AddrDef->Reg;
3329     } else if (AddrDef->MI->getOpcode() == AMDGPU::G_PTR_ADD) {
3331           getSrcRegIgnoringCopies(AddrDef->MI->getOperand(1).getReg(), *MRI);
3333         Register PtrBaseOffset = AddrDef->MI->getOperand(2).getReg();
4424   auto AddrDef = getDefSrcRegIgnoringCopies(Addr, *MRI);
4425   if (AddrDef->MI->getOpcode() == AMDGPU::G_PTR_ADD) {
4428         getSrcRegIgnoringCopies(AddrDef->MI->getOperand(1).getReg(), *MRI);
4431       Register PtrBaseOffset = AddrDef->MI->getOperand(2).getReg();
4451   if (AddrDef->MI->getOpcode() == AMDGPU::G_IMPLICIT_DEF ||
4452       AddrDef->MI->getOpcode() == AMDGPU::G_CONSTANT || !isSGPR(AddrDef->Reg))
4465       [=](MachineInstrBuilder &MIB) { MIB.addReg(AddrDef->Reg); }, // saddr
4489   auto AddrDef = getDefSrcRegIgnoringCopies(Addr, *MRI);
4490   if (AddrDef->MI->getOpcode() == AMDGPU::G_FRAME_INDEX) {
4491     int FI = AddrDef->MI->getOperand(1).getIndex();
4498   Register SAddr = AddrDef->Reg;
4500   if (AddrDef->MI->getOpcode() == AMDGPU::G_PTR_ADD) {
4501     Register LHS = AddrDef->MI->getOperand(1).getReg();
4502     Register RHS = AddrDef->MI->getOperand(2).getReg();
4566   auto AddrDef = getDefSrcRegIgnoringCopies(Addr, *MRI);
4567   if (AddrDef->MI->getOpcode() != AMDGPU::G_PTR_ADD)
4570   Register RHS = AddrDef->MI->getOperand(2).getReg();
4574   Register LHS = AddrDef->MI->getOperand(1).getReg();