Lines Matching defs:N0
3523 SDValue N0 = Op.getOperand(0);
3526 if (N0.getValueType() == MVT::f32)
3527 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0);
3534 assert(N0.getSimpleValueType() == MVT::f64);
3542 SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0);
3910 SDValue N0 = N->getOperand(0);
3914 if (N0.getOpcode() == ISD::TRUNCATE) {
3919 SDValue Src = N0.getOperand(0);
4235 SDValue N0, SDValue N1, unsigned Size, bool Signed) {
4238 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1);
4244 SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1);
4245 SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1);
4278 SDValue N0 = N->getOperand(0);
4300 if (SDValue MulOper = IsFoldableAdd(N0)) {
4306 SDValue MulVal = DAG.getNode(N->getOpcode(), DL, VT, N0, MulOper);
4307 return DAG.getNode(ISD::ADD, DL, VT, MulVal, N0);
4318 if (N0.getOpcode() == ISD::ANY_EXTEND)
4319 N0 = N0.getOperand(0);
4326 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
4327 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
4329 Mul = getMul24(DAG, DL, N0, N1, Size, false);
4330 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
4331 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
4333 Mul = getMul24(DAG, DL, N0, N1, Size, true);
4353 SDValue N0 = N->getOperand(0);
4360 if (N0.getOpcode() == ISD::ANY_EXTEND)
4361 N0 = N0.getOperand(0);
4370 if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
4371 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
4377 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
4378 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
4387 SDValue Lo = DAG.getNode(LoOpcode, DL, MVT::i32, N0, N1);
4388 SDValue Hi = DAG.getNode(HiOpcode, DL, MVT::i32, N0, N1);
4412 SDValue N0 = N->getOperand(0);
4415 if (!isI24(N0, DAG) || !isI24(N1, DAG))
4418 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
4421 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_I24, DL, MVT::i32, N0, N1);
4445 SDValue N0 = N->getOperand(0);
4448 if (!isU24(N0, DAG) || !isU24(N1, DAG))
4451 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
4454 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_U24, DL, MVT::i32, N0, N1);
4726 bool AMDGPUTargetLowering::shouldFoldFNegIntoSrc(SDNode *N, SDValue N0) {
4731 if (N0.hasOneUse()) {
4737 if (fnegFoldsIntoOp(N0.getNode()) &&
4738 (allUsesHaveSourceMods(N) || !allUsesHaveSourceMods(N0.getNode())))
4748 SDValue N0 = N->getOperand(0);
4751 unsigned Opc = N0.getOpcode();
4753 if (!shouldFoldFNegIntoSrc(N, N0))
4759 if (!mayIgnoreSignedZero(N0))
4763 SDValue LHS = N0.getOperand(0);
4764 SDValue RHS = N0.getOperand(1);
4776 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags());
4779 if (!N0.hasOneUse())
4780 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
4787 SDValue LHS = N0.getOperand(0);
4788 SDValue RHS = N0.getOperand(1);
4797 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags());
4800 if (!N0.hasOneUse())
4801 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
4807 if (!mayIgnoreSignedZero(N0))
4811 SDValue LHS = N0.getOperand(0);
4812 SDValue MHS = N0.getOperand(1);
4813 SDValue RHS = N0.getOperand(2);
4830 if (!N0.hasOneUse())
4831 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
4847 SDValue LHS = N0.getOperand(0);
4848 SDValue RHS = N0.getOperand(1);
4859 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags());
4862 if (!N0.hasOneUse())
4863 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
4869 Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags());
4871 SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags());
4875 if (!N0.hasOneUse()) {
4877 DAG.ReplaceAllUsesWith(N0, Neg);
4896 SDValue CvtSrc = N0.getOperand(0);
4903 if (!N0.hasOneUse())
4909 return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags());
4912 SDValue CvtSrc = N0.getOperand(0);
4917 CvtSrc.getOperand(0), N0.getOperand(1));
4920 if (!N0.hasOneUse())
4925 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1));
4933 SDValue Src = N0.getOperand(0);
4948 SDValue BCSrc = N0.getOperand(0);
4976 if (!N0.hasOneUse())
4977 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Result));
5010 SDValue N0 = N->getOperand(0);
5012 if (!N0.hasOneUse())
5015 switch (N0.getOpcode()) {
5019 SDValue Src = N0.getOperand(0);
5254 SDValue N0 = N->getOperand(0);
5261 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6007 Register N0, Register N1) const {
6008 return MRI.hasOneNonDBGUse(N0); // FIXME: handle regbanks