Lines Matching defs:DestVT

1019 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
1026   return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
3354   EVT DestVT = Op.getValueType();
3359     if (DestVT == MVT::f16)
3365     return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext);
3368   if (DestVT == MVT::bf16) {
3378   if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
3390   if (DestVT == MVT::f32)
3393   assert(DestVT == MVT::f64);
3399   EVT DestVT = Op.getValueType();
3405     if (DestVT == MVT::f16)
3411     return DAG.getNode(ISD::SINT_TO_FP, DL, DestVT, Ext);
3414   if (DestVT == MVT::bf16) {
3426   if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
3439   if (DestVT == MVT::f32)
3442   assert(DestVT == MVT::f64);
3625   EVT DestVT = Op.getValueType();
3628   if (SrcVT == MVT::f16 && DestVT == MVT::i16)
3634     return DAG.getNode(Op.getOpcode(), DL, DestVT, PromotedSrc);
3638   if (DestVT == MVT::i16 && (SrcVT == MVT::f32 || SrcVT == MVT::f64)) {
3645   if (DestVT != MVT::i64)
5053     EVT DestVT = N->getValueType(0);
5060     if (DestVT.isVector()) {
5064            isOperationLegal(ISD::BUILD_VECTOR, DestVT))) {
5066         unsigned NElts = DestVT.getVectorNumElements();
5069           EVT DestEltVT = DestVT.getVectorElementType();
5078           return DAG.getBuildVector(DestVT, SL, CastedElts);
5083     if (DestVT.getSizeInBits() != 64 || !DestVT.isVector())
5097       return DAG.getNode(ISD::BITCAST, SL, DestVT, BV);
5108       return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec);