Lines Matching defs:AMDGPUTargetLowering
40 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
51 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) {
55 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) {
61 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
629 bool AMDGPUTargetLowering::mayIgnoreSignedZero(SDValue Op) const {
756 bool AMDGPUTargetLowering::allUsesHaveSourceMods(const SDNode *N,
782 EVT AMDGPUTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
793 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
797 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
803 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
811 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
816 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
856 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy, EVT CastTy,
880 bool AMDGPUTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
884 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
888 bool AMDGPUTargetLowering::isSDNodeAlwaysUniform(const SDNode *N) const {
908 SDValue AMDGPUTargetLowering::getNegatedExpression(
943 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
951 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
958 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT,
964 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {
976 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
985 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
997 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
1007 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
1019 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
1029 bool AMDGPUTargetLowering::isDesirableToCommuteWithShift(
1146 void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(
1264 SDValue AMDGPUTargetLowering::LowerReturn(
1281 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1286 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1291 SDValue AMDGPUTargetLowering::addTokenForArgument(SDValue Chain,
1325 SDValue AMDGPUTargetLowering::lowerUnhandledCall(CallLoweringInfo &CLI,
1352 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
1357 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1368 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
1416 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
1456 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
1507 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
1542 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
1595 SDValue AMDGPUTargetLowering::combineFMinMaxLegacyImpl(
1664 SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT,
1703 AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {
1717 SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {
1725 SDValue AMDGPUTargetLowering::getHiHalf64(SDValue Op, SelectionDAG &DAG) const {
1737 AMDGPUTargetLowering::getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const {
1752 AMDGPUTargetLowering::splitVector(const SDValue &N, const SDLoc &DL,
1767 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1827 SDValue AMDGPUTargetLowering::WidenOrSplitVectorLoad(SDValue Op,
1861 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1905 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
2020 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
2234 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
2289 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
2350 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
2364 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
2404 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
2450 SDValue AMDGPUTargetLowering::LowerFROUNDEVEN(SDValue Op,
2478 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op,
2487 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
2498 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2525 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2574 bool AMDGPUTargetLowering::allowApproxFunc(const SelectionDAG &DAG,
2582 bool AMDGPUTargetLowering::needsDenormHandlingF32(const SelectionDAG &DAG,
2591 SDValue AMDGPUTargetLowering::getIsLtSmallestNormal(SelectionDAG &DAG,
2609 SDValue AMDGPUTargetLowering::getIsFinite(SelectionDAG &DAG, SDValue Src,
2626 AMDGPUTargetLowering::getScaledLogInput(SelectionDAG &DAG, const SDLoc SL,
2649 SDValue AMDGPUTargetLowering::LowerFLOG2(SDValue Op, SelectionDAG &DAG) const {
2690 SDValue AMDGPUTargetLowering::LowerFLOGCommon(SDValue Op,
2787 SDValue AMDGPUTargetLowering::LowerFLOG10(SDValue Op, SelectionDAG &DAG) const {
2793 SDValue AMDGPUTargetLowering::LowerFLOGUnsafe(SDValue Src, const SDLoc &SL,
2832 SDValue AMDGPUTargetLowering::lowerFEXP2(SDValue Op, SelectionDAG &DAG) const {
2883 SDValue AMDGPUTargetLowering::lowerFEXPUnsafe(SDValue X, const SDLoc &SL,
2923 SDValue AMDGPUTargetLowering::lowerFEXP10Unsafe(SDValue X, const SDLoc &SL,
2975 SDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const {
3116 SDValue AMDGPUTargetLowering::lowerCTLZResults(SDValue Op,
3146 SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const {
3206 SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,
3332 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
3351 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
3397 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
3446 SDValue AMDGPUTargetLowering::LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG,
3521 SDValue AMDGPUTargetLowering::LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const {
3620 SDValue AMDGPUTargetLowering::LowerFP_TO_INT(const SDValue Op,
3664 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
3692 return AMDGPUTargetLowering::numBitsUnsigned(Op, DAG) <= 24;
3699 AMDGPUTargetLowering::numBitsSigned(Op, DAG) <= 24;
3776 bool AMDGPUTargetLowering::shouldCombineMemoryType(EVT VT) const {
3797 SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,
3850 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
3907 SDValue AMDGPUTargetLowering::performAssertSZExtCombine(SDNode *N,
3930 SDValue AMDGPUTargetLowering::performIntrinsicWOChainCombine(
3966 SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(
3989 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
4057 SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
4092 SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
4140 SDValue AMDGPUTargetLowering::performTruncateCombine(
4259 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
4344 AMDGPUTargetLowering::performMulLoHiCombine(SDNode *N,
4393 SDValue AMDGPUTargetLowering::performMulhsCombine(SDNode *N,
4426 SDValue AMDGPUTargetLowering::performMulhuCombine(SDNode *N,
4459 SDValue AMDGPUTargetLowering::getFFBX_U32(SelectionDAG &DAG,
4486 SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond,
4543 AMDGPUTargetLowering::foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
4553 if (!AMDGPUTargetLowering::allUsesHaveSourceMods(N.getNode()))
4601 if (!AMDGPUTargetLowering::allUsesHaveSourceMods(N.getNode()))
4620 SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
4679 AMDGPUTargetLowering::getConstantNegateCost(const ConstantFPSDNode *C) const {
4689 bool AMDGPUTargetLowering::isConstantCostlierToNegate(SDValue N) const {
4695 bool AMDGPUTargetLowering::isConstantCheaperToNegate(SDValue N) const {
4726 bool AMDGPUTargetLowering::shouldFoldFNegIntoSrc(SDNode *N, SDValue N0) {
4745 SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
5007 SDValue AMDGPUTargetLowering::performFAbsCombine(SDNode *N,
5032 SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,
5044 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
5291 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
5327 SDValue AMDGPUTargetLowering::loadStackInputValue(SelectionDAG &DAG,
5343 SDValue AMDGPUTargetLowering::storeStackInputValue(SelectionDAG &DAG,
5362 SDValue AMDGPUTargetLowering::loadInputValue(SelectionDAG &DAG,
5383 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
5402 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
5410 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
5577 SDValue AMDGPUTargetLowering::getSqrtEstimate(SDValue Operand,
5595 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
5629 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
5794 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
5855 unsigned AMDGPUTargetLowering::computeNumSignBitsForTargetInstr(
5892 bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
6006 bool AMDGPUTargetLowering::isReassocProfitable(MachineRegisterInfo &MRI,
6012 AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
6042 bool AMDGPUTargetLowering::shouldSinkOperands(