Lines Matching defs:SU
87 // not an SU maps to a given SchedGroup. It contains complementary data
143 // Try to add and edge from SU A to SU B.
157 // Returns true if SU can be added to this SchedGroup.
158 bool canAddSU(SUnit &SU) const;
160 // Add DAG dependencies from all SUnits in this SchedGroup and this SU. If
161 // MakePred is true, SU will be a predecessor of the SUnits in this
162 // SchedGroup, otherwise SU will be a successor.
163 void link(SUnit &SU, bool MakePred = false);
167 int link(SUnit &SU, bool MakePred,
170 // Add DAG dependencies from all SUnits in this SchedGroup and this SU.
171 // Use the predicate to determine whether SU should be a predecessor (P =
173 void link(SUnit &SU, function_ref<bool(const SUnit *A, const SUnit *B)> P);
190 // Returns true if the SU matches all rules
191 bool allowedByRules(const SUnit *SU,
194 if (!Rule.get()->apply(SU, Collection, SyncPipe))
200 // Add SU to the SchedGroup.
201 void add(SUnit &SU) {
204 << *SU.getInstr());
205 Collection.push_back(&SU);
244 static void resetEdges(SUnit &SU, ScheduleDAGInstrs *DAG) {
245 assert(SU.getInstr()->getOpcode() == AMDGPU::SCHED_BARRIER ||
246 SU.getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER ||
247 SU.getInstr()->getOpcode() == AMDGPU::IGLP_OPT);
249 while (!SU.Preds.empty())
250 for (auto &P : SU.Preds)
251 SU.removePred(P);
253 while (!SU.Succs.empty())
254 for (auto &S : SU.Succs)
256 if (SP.getSUnit() == &SU)
291 // The cost penalty of not assigning a SU to a SchedGroup
309 // The direction in which we process the candidate SchedGroups per SU
322 // Find the best SchedGroup for the current SU using the heuristic given all
340 // Add the edges from the SU to the other SchedGroups in pipeline, and
342 int addEdges(SmallVectorImpl<SchedGroup> &SyncPipeline, SUnit *SU, int SGID,
344 /// Link the pipeline as if \p SU was in the SchedGroup with ID \p SGID. It
348 int linkSUnit(SUnit *SU, int SGID,
397 auto SchedBarr = llvm::find_if(TempCollection, [](SUnit *SU) {
398 return SU->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER;
455 for (auto &SU : SG.Collection) {
456 if (SU->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER)
457 SGBarr = SU;
458 LLVM_DEBUG(dbgs() << "SU(" << SU->NodeNum << ")\n");
476 SUnit *SU, int SGID, std::vector<std::pair<SUnit *, SUnit *>> &AddedEdges,
486 AddedCost += Group.link(*SU, MakePred, AddedEdges);
493 SmallVectorImpl<SchedGroup> &SyncPipeline, SUnit *SU, int SGID,
500 // SU should be linked as a predecessor to SUs in those SchedGroups. The
504 return IsBottomUp ? linkSUnit(SU, SGID, AddedEdges, SyncPipeline.rbegin(),
506 : linkSUnit(SU, SGID, AddedEdges, SyncPipeline.begin(),
631 LLVM_DEBUG(dbgs() << "Fitting SU(" << CurrSU.first->NodeNum
727 LLVM_DEBUG(dbgs() << "Fitting SU(" << CurrSU.first->NodeNum
917 // The number of transitive MFMA successors for each TRANS SU
919 // The number of transitive TRANS predecessors for each MFMA SU
942 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
959 Cache->begin(), Cache->end(), [&SU, &DAG](SUnit *TargetSU) {
960 return DAG->IsReachable(TargetSU, const_cast<SUnit *>(SU));
976 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
1002 return DAG->IsReachable((*Cache)[0], const_cast<SUnit *>(SU));
1018 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
1022 if (!SU || !TII->isMFMAorWMMA(*ChainSeed->getInstr()))
1048 return DAG->IsReachable((*Cache)[0], const_cast<SUnit *>(SU));
1067 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
1073 SU->Succs.begin(), SU->Succs.end(),
1079 for (auto Succ : SU->Succs) {
1108 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
1114 SU->Succs.begin(), SU->Succs.end(),
1120 for (auto Succ : SU->Succs) {
1143 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
1145 auto Opc = SU->getInstr()->getOpcode();
1156 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
1158 return SU->getInstr()->getOpcode() == AMDGPU::V_FMA_F32_e64 ||
1159 SU->getInstr()->getOpcode() == AMDGPU::V_PK_FMA_F32;
1168 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
1170 return SU->getInstr()->getOpcode() == AMDGPU::V_ADD_F32_e32;
1183 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
1201 if (Succ.getSUnit() == SU && Succ.getKind() == SDep::Data)
1220 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
1239 if (DAG->IsReachable(const_cast<SUnit *>(SU), OtherEle))
1249 /// Whether or not the instruction occurs after the SU with NodeNUm \p Number
1255 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
1258 return SU->NodeNum >= Number;
1265 /// Whether or not the SU is exactly the \p Number th MFMA in the chain
1273 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
1275 if (!SU || !TII->isMFMAorWMMA(*ChainSeed->getInstr()))
1301 return (*Cache)[0] == SU;
1315 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
1321 for (auto &SU : DAG->SUnits)
1322 if (TII->isTRANS(SU.getInstr()->getOpcode())) {
1323 Cache->push_back(&SU);
1330 return SU->NodeNum > (*Cache)[0]->NodeNum;
1382 for (SUnit &SU : DAG->SUnits) {
1383 auto Opc = SU.getInstr()->getOpcode();
1386 if (SU.Succs.size() >= 7)
1388 for (auto &Succ : SU.Succs) {
1392 ExpPipeCands.push_back(&SU);
1395 if (TII->isMFMAorWMMA(*SU.getInstr()))
1396 MFMAPipeCands.push_back(&SU);
1399 PackSUs.push_back(&SU);
1402 CvtSUs.push_back(&SU);
1859 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
1878 if (DAG->IsReachable(Elt, const_cast<SUnit *>(SU)))
1892 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
1894 auto MI = SU->getInstr();
1901 for (auto &Succ : SU->Succs) {
1916 return llvm::any_of(*Cache, [&SU](SUnit *Elt) {
1917 return llvm::any_of(SU->Succs, [&Elt](const SDep &ThisSucc) {
1927 // Whether the SU is a successor of any element in previous SchedGroup
1930 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
1946 OtherGroup->Collection.end(), [&SU](SUnit *Elt) {
1949 [&SU](SDep &Succ) {
1950 return Succ.getSUnit() == SU;
1962 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
1964 auto MI = SU->getInstr();
1996 /// Whether the SU shares a V_PERM predecessor with any SU in the SchedGroup
2003 bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
2038 return llvm::any_of(*Cache, [&SU, &DAG](SUnit *Elt) {
2039 return DAG->IsReachable(const_cast<SUnit *>(SU), Elt);
2081 for (auto &SU : DAG->SUnits) {
2082 auto I = SU.getInstr();
2090 for (auto Pred : SU.Preds) {
2093 DSWithPerms.push_back(&SU);
2343 void addSchedBarrierEdges(SUnit &SU);
2360 bool initIGLPOpt(SUnit &SU);
2448 int SchedGroup::link(SUnit &SU, bool MakePred,
2452 SUnit *B = &SU;
2473 void SchedGroup::link(SUnit &SU, bool MakePred) {
2475 SUnit *B = &SU;
2485 void SchedGroup::link(SUnit &SU,
2488 SUnit *B = &SU;
2501 bool SchedGroup::canAddSU(SUnit &SU) const {
2502 MachineInstr &MI = *SU.getInstr();
2517 for (auto &SU : DAG->SUnits) {
2521 if (canAddSU(SU))
2522 add(SU);
2530 auto &SU = *RIter;
2534 if (canAddSU(SU))
2535 SyncedInstrs[&SU].push_back(SGID);
2547 auto &SU = *I;
2550 if (canAddSU(SU))
2551 SyncedInstrs[&SU].push_back(SGID);
2672 bool IGroupLPDAGMutation::initIGLPOpt(SUnit &SU) {
2674 (IGLPStrategyID)SU.getInstr()->getOperand(0).getImm();