Lines Matching defs:MFMA

71   MFMA = 1u << 3,
79   ALL = ALU | VALU | SALU | MFMA | VMEM | VMEM_READ | VMEM_WRITE | DS |
265 // {VMEM_READ, VALU, MFMA, VMEM_READ} and we encounter a VMEM_READ instruction
888   // Count the number of MFMA instructions.
902         SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII);
913   // The count of MFMA SUs involved in the interleaved pipeline
917   // The number of transitive MFMA successors for each TRANS SU
919   // The number of transitive TRANS predecessors for each MFMA SU
921   // The count of independent "chains" of MFMA instructions in the pipeline
923   // The length of each independent "chain" of MFMA instructions
930   // The first occuring DS_READ which feeds an MFMA chain
932   // The MFMAPipe SUs with no MFMA predecessors
938   /// Whether or not the instruction is a transitive predecessor of an MFMA
970   /// \p Number th MFMA of the MFMAs occuring after a TRANS instruction
1010   /// Whether or not the instruction enables the exact MFMA that is the \p
1011   /// Number th MFMA in the chain starting with \p ChainSeed
1265   /// Whether or not the SU is exactly the \p Number th MFMA in the chain
1385       // Avoid counting a potential bonus V_EXP which all the MFMA depend on
1415   // Count the number of EXPs that reach an MFMA
1509   // The number of bit pack operations an MFMA depends on
1539   // The number of V_EXPs required to resolve all dependencies for an MFMA
1721   // The "extra" EXP which enables all MFMA
1756     // Round N MFMA
1758         SchedGroupMask::MFMA, MFMARatio, PipelineSyncID, DAG, TII);
1848       SchedGroupMask::MFMA, MFMAEnablement * 2, PipelineSyncID, DAG, TII);
1856   // Whether the DS_READ is a predecessor of first four MFMA in region
2163           SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII);
2173   // Phase 1: Break up DS_READ and MFMA clusters.
2174   // First DS_READ to make ready initial MFMA, then interleave MFMA with DS_READ
2177   // Make ready initial MFMA
2184       SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII);
2187   // Interleave MFMA with DS_READ prefetch
2194         SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII);
2200   // depend on. Interleave MFMA to keep XDL unit busy throughout.
2220         SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII);
2231         SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII);
2237   // Interleave MFMA to keep XDL unit busy throughout.
2249         SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII);
2256   // depend on. Interleave MFMA to keep XDL unit busy throughout.
2270         SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII);
2284         SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII);
2295         SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII);
2306         SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII);
2407   else if (((SGMask & SchedGroupMask::MFMA) != SchedGroupMask::NONE) &&
2622   // ALU implies VALU, SALU, MFMA, TRANS.
2625                     ~SchedGroupMask::MFMA & ~SchedGroupMask::TRANS;
2626   // VALU, SALU, MFMA, TRANS implies ALU.
2629            (InvertedMask & SchedGroupMask::MFMA) == SchedGroupMask::NONE ||