Lines Matching +full:use +full:- +full:case
1 //=== lib/CodeGen/GlobalISel/AMDGPUCombinerHelper.cpp ---------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
23 case AMDGPU::G_FADD:
24 case AMDGPU::G_FSUB:
25 case AMDGPU::G_FMUL:
26 case AMDGPU::G_FMA:
27 case AMDGPU::G_FMAD:
28 case AMDGPU::G_FMINNUM:
29 case AMDGPU::G_FMAXNUM:
30 case AMDGPU::G_FMINNUM_IEEE:
31 case AMDGPU::G_FMAXNUM_IEEE:
32 case AMDGPU::G_FMINIMUM:
33 case AMDGPU::G_FMAXIMUM:
34 case AMDGPU::G_FSIN:
35 case AMDGPU::G_FPEXT:
36 case AMDGPU::G_INTRINSIC_TRUNC:
37 case AMDGPU::G_FPTRUNC:
38 case AMDGPU::G_FRINT:
39 case AMDGPU::G_FNEARBYINT:
40 case AMDGPU::G_INTRINSIC_ROUND:
41 case AMDGPU::G_INTRINSIC_ROUNDEVEN:
42 case AMDGPU::G_FCANONICALIZE:
43 case AMDGPU::G_AMDGPU_RCP_IFLAG:
44 case AMDGPU::G_AMDGPU_FMIN_LEGACY:
45 case AMDGPU::G_AMDGPU_FMAX_LEGACY:
47 case AMDGPU::G_INTRINSIC: {
50 case Intrinsic::amdgcn_rcp:
51 case Intrinsic::amdgcn_rcp_legacy:
52 case Intrinsic::amdgcn_sin:
53 case Intrinsic::amdgcn_fmul_legacy:
54 case Intrinsic::amdgcn_fmed3:
55 case Intrinsic::amdgcn_fma_legacy:
66 /// \p returns true if the operation will definitely need to use a 64-bit
67 /// encoding, and thus will use a VOP3 encoding regardless of the source
83 case AMDGPU::COPY:
84 case AMDGPU::G_SELECT:
85 case AMDGPU::G_FDIV:
86 case AMDGPU::G_FREM:
87 case TargetOpcode::INLINEASM:
88 case TargetOpcode::INLINEASM_BR:
89 case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS:
90 case AMDGPU::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
91 case AMDGPU::G_BITCAST:
92 case AMDGPU::G_ANYEXT:
93 case AMDGPU::G_BUILD_VECTOR:
94 case AMDGPU::G_BUILD_VECTOR_TRUNC:
95 case AMDGPU::G_PHI:
97 case AMDGPU::G_INTRINSIC:
98 case AMDGPU::G_INTRINSIC_CONVERGENT: {
101 case Intrinsic::amdgcn_interp_p1:
102 case Intrinsic::amdgcn_interp_p2:
103 case Intrinsic::amdgcn_interp_mov:
104 case Intrinsic::amdgcn_interp_p1_f16:
105 case Intrinsic::amdgcn_interp_p2_f16:
106 case Intrinsic::amdgcn_div_scale:
119 // Some users (such as 3-operand FMA/MAD) must use a VOP3 encoding, and thus
120 // it is truly free to use a source modifier in all cases. If there are
126 for (const MachineInstr &Use : MRI.use_nodbg_instructions(Dst)) {
127 if (!hasSourceMods(Use))
130 if (!opMustUseVOP3Encoding(Use, MRI)) {
139 const TargetOptions &Options = MI.getMF()->getTarget().Options;
159 if (FPValReg->Value.isZero() && !FPValReg->Value.isNegative())
162 const GCNSubtarget &ST = MI.getMF()->getSubtarget<GCNSubtarget>();
163 if (ST.hasInv2PiInlineImm() && isInv2Pi(FPValReg->Value))
171 case AMDGPU::G_FMAXNUM:
173 case AMDGPU::G_FMINNUM:
175 case AMDGPU::G_FMAXNUM_IEEE:
177 case AMDGPU::G_FMINNUM_IEEE:
179 case AMDGPU::G_FMAXIMUM:
181 case AMDGPU::G_FMINIMUM:
183 case AMDGPU::G_AMDGPU_FMAX_LEGACY:
185 case AMDGPU::G_AMDGPU_FMIN_LEGACY:
211 switch (MatchInfo->getOpcode()) {
212 case AMDGPU::G_FMINNUM:
213 case AMDGPU::G_FMAXNUM:
214 case AMDGPU::G_FMINNUM_IEEE:
215 case AMDGPU::G_FMAXNUM_IEEE:
216 case AMDGPU::G_FMINIMUM:
217 case AMDGPU::G_FMAXIMUM:
218 case AMDGPU::G_AMDGPU_FMIN_LEGACY:
219 case AMDGPU::G_AMDGPU_FMAX_LEGACY:
222 MatchInfo->getOperand(2).getReg(), MRI);
223 case AMDGPU::G_FADD:
224 case AMDGPU::G_FSUB:
225 case AMDGPU::G_FMA:
226 case AMDGPU::G_FMAD:
228 case AMDGPU::G_FMUL:
229 case AMDGPU::G_FPEXT:
230 case AMDGPU::G_INTRINSIC_TRUNC:
231 case AMDGPU::G_FPTRUNC:
232 case AMDGPU::G_FRINT:
233 case AMDGPU::G_FNEARBYINT:
234 case AMDGPU::G_INTRINSIC_ROUND:
235 case AMDGPU::G_INTRINSIC_ROUNDEVEN:
236 case AMDGPU::G_FSIN:
237 case AMDGPU::G_FCANONICALIZE:
238 case AMDGPU::G_AMDGPU_RCP_IFLAG:
240 case AMDGPU::G_INTRINSIC:
241 case AMDGPU::G_INTRINSIC_CONVERGENT: {
242 Intrinsic::ID IntrinsicID = cast<GIntrinsic>(MatchInfo)->getIntrinsicID();
244 case Intrinsic::amdgcn_rcp:
245 case Intrinsic::amdgcn_rcp_legacy:
246 case Intrinsic::amdgcn_sin:
247 case Intrinsic::amdgcn_fmul_legacy:
248 case Intrinsic::amdgcn_fmed3:
250 case Intrinsic::amdgcn_fma_legacy:
269 // (if %A has one use, specifically fneg above)
302 switch (MatchInfo->getOpcode()) {
303 case AMDGPU::G_FADD:
304 case AMDGPU::G_FSUB:
305 NegateOperand(MatchInfo->getOperand(1));
306 NegateOperand(MatchInfo->getOperand(2));
308 case AMDGPU::G_FMUL:
309 NegateEitherOperand(MatchInfo->getOperand(1), MatchInfo->getOperand(2));
311 case AMDGPU::G_FMINNUM:
312 case AMDGPU::G_FMAXNUM:
313 case AMDGPU::G_FMINNUM_IEEE:
314 case AMDGPU::G_FMAXNUM_IEEE:
315 case AMDGPU::G_FMINIMUM:
316 case AMDGPU::G_FMAXIMUM:
317 case AMDGPU::G_AMDGPU_FMIN_LEGACY:
318 case AMDGPU::G_AMDGPU_FMAX_LEGACY: {
319 NegateOperand(MatchInfo->getOperand(1));
320 NegateOperand(MatchInfo->getOperand(2));
321 unsigned Opposite = inverseMinMax(MatchInfo->getOpcode());
325 case AMDGPU::G_FMA:
326 case AMDGPU::G_FMAD:
327 NegateEitherOperand(MatchInfo->getOperand(1), MatchInfo->getOperand(2));
328 NegateOperand(MatchInfo->getOperand(3));
330 case AMDGPU::G_FPEXT:
331 case AMDGPU::G_INTRINSIC_TRUNC:
332 case AMDGPU::G_FRINT:
333 case AMDGPU::G_FNEARBYINT:
334 case AMDGPU::G_INTRINSIC_ROUND:
335 case AMDGPU::G_INTRINSIC_ROUNDEVEN:
336 case AMDGPU::G_FSIN:
337 case AMDGPU::G_FCANONICALIZE:
338 case AMDGPU::G_AMDGPU_RCP_IFLAG:
339 case AMDGPU::G_FPTRUNC:
340 NegateOperand(MatchInfo->getOperand(1));
342 case AMDGPU::G_INTRINSIC:
343 case AMDGPU::G_INTRINSIC_CONVERGENT: {
344 Intrinsic::ID IntrinsicID = cast<GIntrinsic>(MatchInfo)->getIntrinsicID();
346 case Intrinsic::amdgcn_rcp:
347 case Intrinsic::amdgcn_rcp_legacy:
348 case Intrinsic::amdgcn_sin:
349 NegateOperand(MatchInfo->getOperand(2));
351 case Intrinsic::amdgcn_fmul_legacy:
352 NegateEitherOperand(MatchInfo->getOperand(2), MatchInfo->getOperand(3));
354 case Intrinsic::amdgcn_fmed3:
355 NegateOperand(MatchInfo->getOperand(2));
356 NegateOperand(MatchInfo->getOperand(3));
357 NegateOperand(MatchInfo->getOperand(4));
359 case Intrinsic::amdgcn_fma_legacy:
360 NegateEitherOperand(MatchInfo->getOperand(2), MatchInfo->getOperand(3));
361 NegateOperand(MatchInfo->getOperand(4));
373 Register MatchInfoDst = MatchInfo->getOperand(0).getReg();
376 // MatchInfo now has negated value so use that instead of old Dst.
384 replaceRegOpWith(MRI, MatchInfo->getOperand(0), NegatedMatchInfo);
386 // MatchInfo now has negated value so use that instead of old Dst.
390 auto NextInst = ++MatchInfo->getIterator();
403 if (Def->getOpcode() == TargetOpcode::G_FPEXT) {
404 Register SrcReg = Def->getOperand(1).getReg();
408 if (Def->getOpcode() == TargetOpcode::G_FCONSTANT) {
409 APFloat Val = Def->getOperand(1).getFPImm()->getValueAPF();