Lines Matching defs:MIRBuilder
39 return Handler.MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0);
81 ExtReg = MIRBuilder.buildPtrToInt(S32, ExtReg).getReg(0);
83 ExtReg = MIRBuilder.buildBitcast(S32, ExtReg).getReg(0);
86 auto ToSGPR = MIRBuilder
93 MIRBuilder.buildCopy(PhysReg, ExtReg);
107 auto &MFI = MIRBuilder.getMF().getFrameInfo();
113 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
114 auto AddrReg = MIRBuilder.buildFrameIndex(
127 auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg);
133 MIRBuilder.buildTrunc(ValVReg, Extended);
143 MachineFunction &MF = MIRBuilder.getMF();
148 MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
162 MIRBuilder.getMBB().addLiveIn(PhysReg);
167 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
169 : AMDGPUIncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {}
188 AMDGPUOutgoingArgHandler(MachineIRBuilder &MIRBuilder,
191 : AMDGPUOutgoingValueHandler(MIRBuilder, MRI, MIB), FPDiff(FPDiff),
197 MachineFunction &MF = MIRBuilder.getMF();
204 auto FIReg = MIRBuilder.buildFrameIndex(PtrTy, FI);
212 const GCNSubtarget &ST = MIRBuilder.getMF().getSubtarget<GCNSubtarget>();
215 SPReg = MIRBuilder.buildCopy(PtrTy,
221 SPReg = MIRBuilder.buildInstr(AMDGPU::G_AMDGPU_WAVE_ADDRESS, {PtrTy},
226 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset);
228 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg);
237 MIRBuilder.buildCopy(PhysReg, ExtReg);
243 MachineFunction &MF = MIRBuilder.getMF();
250 MIRBuilder.buildStore(ValVReg, Addr, *MMO);
750 bool AMDGPUCallLowering::passSpecialInputs(MachineIRBuilder &MIRBuilder,
754 MachineFunction &MF = MIRBuilder.getMF();
823 LI->loadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy);
825 LI->getImplicitArgPtr(InputReg, MRI, MIRBuilder);
830 MIRBuilder.buildConstant(InputReg, *Id);
832 MIRBuilder.buildUndef(InputReg);
837 MIRBuilder.buildUndef(InputReg);
890 LI->loadInputValue(InputReg, MIRBuilder, IncomingArgX,
893 InputReg = MIRBuilder.buildConstant(S32, 0).getReg(0);
900 LI->loadInputValue(Y, MIRBuilder, IncomingArgY, std::get<1>(WorkitemIDY),
903 Y = MIRBuilder.buildShl(S32, Y, MIRBuilder.buildConstant(S32, 10)).getReg(0);
904 InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Y).getReg(0) : Y;
910 LI->loadInputValue(Z, MIRBuilder, IncomingArgZ, std::get<1>(WorkitemIDZ),
913 Z = MIRBuilder.buildShl(S32, Z, MIRBuilder.buildConstant(S32, 20)).getReg(0);
914 InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Z).getReg(0) : Z;
925 MIRBuilder.buildUndef(InputReg);
932 LI->loadInputValue(InputReg, MIRBuilder, &IncomingArg,
977 MachineIRBuilder &MIRBuilder,
986 auto Ptr = MIRBuilder.buildGlobalValue(
1156 MachineIRBuilder &MIRBuilder, MachineInstrBuilder &CallInst,
1163 auto ScratchRSrcReg = MIRBuilder.buildCopy(LLT::fixed_vector(4, 32),
1170 MIRBuilder.buildCopy(CalleeRSrcReg, ScratchRSrcReg);
1175 MIRBuilder.buildCopy((Register)ArgReg.first, ArgReg.second);
1181 MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
1183 MachineFunction &MF = MIRBuilder.getMF();
1201 CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP);
1205 auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1206 if (!addCallTargetOperands(MIB, MIRBuilder, Info))
1290 if (!passSpecialInputs(MIRBuilder, CCInfo, ImplicitArgRegs, Info))
1300 AMDGPUOutgoingArgHandler Handler(MIRBuilder, MRI, MIB, true, FPDiff);
1301 if (!handleAssignments(Handler, OutArgs, CCInfo, ArgLocs, MIRBuilder))
1307 handleImplicitCallArguments(MIRBuilder, MIB, ST, *FuncInfo, CalleeCC,
1319 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN).addImm(NumBytes).addImm(0);
1323 MIRBuilder.insertInstr(MIB);
1343 bool AMDGPUCallLowering::lowerChainCall(MachineIRBuilder &MIRBuilder,
1354 MachineFunction &MF = MIRBuilder.getMF();
1386 return lowerTailCall(MIRBuilder, Info, OutArgs);
1389 bool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
1395 return lowerChainCall(MIRBuilder, Info);
1403 MachineFunction &MF = MIRBuilder.getMF();
1422 isEligibleForTailCallOptimization(MIRBuilder, Info, InArgs, OutArgs);
1432 return lowerTailCall(MIRBuilder, Info, OutArgs);
1440 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP)
1449 auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1455 if (!addCallTargetOperands(MIB, MIRBuilder, Info))
1472 if (!passSpecialInputs(MIRBuilder, CCInfo, ImplicitArgRegs, Info))
1483 AMDGPUOutgoingArgHandler Handler(MIRBuilder, MRI, MIB, false);
1484 if (!handleAssignments(Handler, OutArgs, CCInfo, ArgLocs, MIRBuilder))
1492 handleImplicitCallArguments(MIRBuilder, MIB, ST, *MFI, Info.CallConv,
1512 MIRBuilder.insertInstr(MIB);
1521 CallReturnHandler Handler(MIRBuilder, MRI, MIB);
1522 if (!determineAndHandleAssignments(Handler, Assigner, InArgs, MIRBuilder,
1529 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN)
1534 insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs,